News Article
MOSIS announces IBM's SOI technology
IBM’s 12SO 45nm SOI process technology available in low volume MPW service.
The MOSIS Service announced the availability of multiple project wafer (MPW) low volume fabrication services using IBM’s sixth generation silicon on insulator (SOI) 12SO technology. System on chip designers (SoC) requiring integration, high speed and low power consumption will now have access to the 45 nanometre CMOS SOI process. Aimed at large SoC applications requiring a high gate count, the SOI technology provides low leakage and higher performance improvement, typically 30%, when compared to bulk silicon. Power reduction gain is in the range of 40%.
Deputy director of MOSIS, Wes Hansford, commented, “As the industry’s first 45nm SOI process, this energy saving SOI process is suitable for a broad range of consumer electronics applications such as digital TVs and high end mobile applications. By using our MPW services, organisations can dramatically reduce the cost of sampling devices by having access to this leading edge semiconductor process in low volumes. Multiple designs are aggregated onto one mask set allowing customers to share the overhead costs associated with mask creation, fabrication and assembly.”
A Cadence design kit including CAD tool support files, DRC and LVS decks, and simulation files are available. Design rules, process specifications and SPICE parameters are also provided.
Deputy director of MOSIS, Wes Hansford, commented, “As the industry’s first 45nm SOI process, this energy saving SOI process is suitable for a broad range of consumer electronics applications such as digital TVs and high end mobile applications. By using our MPW services, organisations can dramatically reduce the cost of sampling devices by having access to this leading edge semiconductor process in low volumes. Multiple designs are aggregated onto one mask set allowing customers to share the overhead costs associated with mask creation, fabrication and assembly.”
A Cadence design kit including CAD tool support files, DRC and LVS decks, and simulation files are available. Design rules, process specifications and SPICE parameters are also provided.
