Integrating 3D potential
The Soitec Group has announced that it has entered into collaboration with IBM to pioneer 22-nanometer (nm) node and beyond silicon wafer substrate and bonding techniques that will enable wafer-level, three-dimensional (3D) integration technology for next-generation integrated circuits (ICs). The two companies have been working together for many years to improve the design and specifications of advanced silicon wafer substrates to meet the needs of IBM’s manufacturing roadmap.
The objective of this new collaboration is to develop highly flexible and cost-effective solutions for wafer-to-wafer stacking, a semiconductor technology designed to yield ICs with faster speeds and higher performance. In joining IBM's 3D integration effort, Soitec will leverage its Smart StackingTM technology and all of its wafer-level bonding expertise including oxide-to-oxide and metal-to-metal molecular bonding—developed in collaboration with CEA/Leti (the Electronics and Information Technology Laboratory of the of the French Atomic Energy Commission).
"This collaboration with Soitec is another step in IBM’s drive to accelerate 3D integration technology, and reinforces the expanding IBM ecosystem of leading companies and research organizations that are working together to achieve significant advances in semiconductor and packaging technology," said Dr. Gary Patton, Vice President, Semiconductor Research and Development Center, IBM. "Through these collaborations, IBM intends to accelerate the development of emerging 3D integration technology and demonstrate the possibilities of achieving higher circuit densities, faster speeds and lower power usage with this vertical integration approach.”
“Soitec has continuously supported IBM’s development programs over the past 15 years with our SOI and other engineered substrates. We expect this new collaboration with IBM will help solve the challenges that IBM is addressing through its 3D program,” said Carlos Mazuré, CTO of Soitec.
