Improved 65nm low power
Chartered Semiconductor Manufacturing has announced the general availability of an enhanced version of its 65-nanometer (nm) low-power (LP) process, called 65nm LPe. The 65nm LPe process utilizes innovative leakage-reduction techniques to significantly improve system-on-chip (SoC) standby power consumption by up to 50 percent. The result is a lower-power process especially suited for battery-operated and cost-sensitive mobile applications that require active standby conditions, such as mobile handsets, multimedia players or personal internet devices. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities.
The 65nm LPe process significantly improves the performance-to-leakage ratio (Ion/Ioff) within the process’ pMOSFET. Given the same Ion (uA/um), the Ioff current is reduced by a magnitude of 20X. This directly impacts the battery life of mobile applications as this leakage improvement is observable in both active and standby situations. In cases where a product operates in long standby situations such as a mobile phone, improvement in the standby power consumption can be as great as 15-25 percent, depending on the application.
A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic. The support includes analog front end (AFE), audio codecs, standard interfaces and a range of level physical IP libraries and memory compilers that have been specifically tuned to take advantage of the enhanced leakage capabilities of the process.
“ARM is pleased to expand our long standing relationship with Chartered by offering a full complement of physical IP optimized for Chartered 65LPe process,” said Simon Segars, executive vice president and general manager PIPD division, ARM. “This rich platform of IP includes enhanced memories and logic targeted at improving the performance of ARM processors. All products are supported by the most advanced power management EDA views. We believe this combination of 65LPe process and ARM physical IP is well suited to a range of mainstream applications where leakage optimization is paramount.