Room for expansion
STATS ChipPAC hasannounced that it is expanding capacity for full turnkey wafer level packaging in its Singapore operation.
Wafer level packages remain one of the highest growth semiconductor packages due to increasing demand in mobile applications requiring the smallest, lightest devices that areable to deliver high performance and reliability. As one of the most compact packaging methods available, wafer level packages differ from laminate and leadframe based packages in that all of the process steps are performed at thewafer level prior to the singulation of the die from the wafer. Full turnkey wafer level packaging includes wafer bump, test and die level services such astape and reel.
STATS ChipPAC has been on a steady production ramp with wafer level packaging services and more than doubled its production volume in 2008. The Company intends to continue to expand its Singapore wafer level operation and is on track to achieve another 50% increase in wafer level capacity by the third quarter of 2009. Singapore has proven to be an excellent logistics choice to support growth in wafer levelpackaging for a number of reasons including its strategic location and close proximity to other countries within Asia, anexperienced workforce and an efficient import and export process.
"Despite the slowdown in the global economy, there continues to be customer demand for high performance packages with the smallest possible form factor. For semiconductor companies interested in converting conventional packages to wafer level packaging solutions to achieve increased functionality and higher input/output performance at a lower cost, the available manufacturing capacityin the market has been limited," said Wan Choong Hoe, Executive Vice President and Chief Operating Officer, STATS Chip PAC. "We are making a focused investment to strategically expand our wafer level capacity to service the growing demand from our customers."
STATS Chip PAC's wafer level packaging solutions include a wide range of technologies for wafer repassivation, redistribution and IPD layers combined with electronics industry preferred lead free SAC alloys in both fine and large pitch applications. Additionally, a complete turnkey process flow is available with flexible backend assembly capability supporting high volume wafer sort, automatic optical inspection and backend processing of bare die into tape and reel or waffle pack.
