AMAT pushes 3D interconnect
Applied Materials is developing technology for through-silicon via (TSV) technology for high-volume manufacturing. Seen as a critical technology for producing the world's future mobile devices, TSV structures connect multiple layers of stacked integrated circuits or chips (3D-ICs) to deliver a higher performance, more functional, smaller form factor package that consumes less power. With today's announcement of the Applied Producer Avila system, Applied Materials becomes the first equipment supplier to offer comprehensive TSV solutions for speeding the development and time to market of 3D-ICs.
According to market researchers, leading chipmakers are making strategic investments in 3D-TSVs, with more than fifteen 300mm pilot lines in operation or under development.1 Applied's wafer-level equipment market opportunity for advanced packaging, including TSV fabrication, is forecast to be nearly US$500 million this year.2
"3D chip stacking with TSV interconnects provides the industry with a compelling solution to chip scaling, but successful implementation of TSVs requires an unprecedented level of cooperation within the supply chain," said Dr. Bart Swinnen, director of Interconnect and Packaging at imec. "Applied is a major contributor in our 3D TSV program where we are developing cost-effective technology solutions that will give an extra dimension to scaling."
One of the keys to fabricating many 3D chip structures is the capability to deposit insulating silicon oxide and nitride films at temperatures less than 200°C. The TSVs in these structures are created on exceptionally thin wafers during the final stages of the manufacturing process, where higher temperatures can damage the adhesive used to bond the wafer to its temporary carrier. Uniquely meeting this challenge, the Avila system provides customers with ultra-uniform, low-temperature PECVD3 films at up to three times the wafer throughput of competing technologies, enabling up to a 30% lower cost-of-ownership. A customer has already qualified the Avila system for pilot production of stacked memory devices.
"Our holistic approach allows us to offer customers a complete toolset for all TSV manufacturing flows encompassing etch, CVD, PVD4, ECD5, wafer cleaning and CMP6," said Dr. Randhir Thakur, executive vice president and general manager of Applied's Silicon Systems Group. "With our unique ability to validate complete process flows at the Maydan Technology Center, Applied can accelerate learning for customers and consortium members, assuring a smooth transition from R&D to volume production."
Applied Materials is closely collaborating with imec to develop new TSV-enabling technologies. Within its multi-partner program on 3D integration, imec develops and validates full 3D technologies including the TSV process, wafer backside processes including thinning and backside deposition and patterning, as well as the actual chip stacking and stack packaging operations. A recent breakthrough is the integration of TSV in 65nm CMOS technology. Applied has played a key role in this achievement which has been realized in partnership with more than 20 semiconductor companies.
