News Article
NVM architecture designer chosen
The University of Tokyo picks Docea Power to design NVM architecture as part of Japanese National Research Program
Docea Power, a design-for-low-power company has announced that its Aceplorer software has been selected by the University of Tokyo to model and optimize power consumption for new non-volatile memory (NVM) designs and architectures as part of a Japanese national research project. The project assesses the effectiveness of a new NVM design architecture developed by the team of Ken Takeuchi, who is an Associate Professor Electrical Engineering, at the University of Tokyo’s Takeuchi Laboratory. The new memory called ReRAM for Resistance-change memory consumes significantly less power during data writing and shows less bit rate failure.
“Our new NVM architecture shows significant advances in terms of speed, power consumption and reliability,” said Professor Ken Takeuchi. “By using Docea’s Aceplorer to model power consumption at the electronic system level (ESL), we can investigate the optimum architecture design and share the power consumption performances with system architects.”
Ghislain Kaiser, CEO of Docea Power added, “At Docea, we are committed to proposing solutions to the IC design community where new challenges of both power consumption and thermal distribution can only be solved at the ESL level in order to allow fast enough what-if analysis and architecture optimization.”
“Our new NVM architecture shows significant advances in terms of speed, power consumption and reliability,” said Professor Ken Takeuchi. “By using Docea’s Aceplorer to model power consumption at the electronic system level (ESL), we can investigate the optimum architecture design and share the power consumption performances with system architects.”
Ghislain Kaiser, CEO of Docea Power added, “At Docea, we are committed to proposing solutions to the IC design community where new challenges of both power consumption and thermal distribution can only be solved at the ESL level in order to allow fast enough what-if analysis and architecture optimization.”
