News Article
Flip chip with copper in mind
STATS releases copper enhanced packaging
STATS ChipPAC announced the fcCuBE technology, an advanced flip chip packaging technology that features copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and Enhanced assembly processes. fcCuBE technology delivers high input/output (I/O) density, high performance and superior reliability in advanced silicon nodes. The fcCuBE technology offers enhanced flip chip packaging with a 20-40% lower cost over standard flip chip packaging, a compelling value with price points comparable to mainstream semiconductor packaging solutions.
“We have taken our innovative Low Cost Flip Chip technology and enhanced it to achieve greater design flexibility and performance across a broader range of applications, I/O requirements and fab nodes. The compatibility of fcCuBE technology with advanced silicon nodes has been proven down to 45/40nm, and early testing at the 28nm silicon node have shown equally promising results. The significance of fcCuBE comes from the combination of advancements we have made in materials, structure and manufacturing process capabilities,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.
fcCuBE technology is based on STATS ChipPAC’s BOL interconnect structure which has been combined with Cu column bump to deliver an ultra high I/O escape routing density with a finer bump pitch compared to standard solder bumps. The advancement enables more relaxed substrate design rules than standard flip chip packaging and provides scalability to very fine bump pitches of 80 micron and below. The fcCuBE solution also offers a reduction of flip chip packaging stress on ELK/ULK structures in advanced silicon nodes and a higher resistance to the electromigration phenomenon which can result from the higher current density induced by the scaling of features.
Dr. Han said, “We are seamlessly deploying the core fcCuBE technology beyond traditional single-die flip chip packaging into more complex stacked/3D packages including Package-on-Package (PoP), Package-in-Package (PiP), flip chip/wire bond hybrid packages and next-generation Through Silicon Via (TSV) configurations.”
