News Article
Non visual inspection
QCept announce development relationship
Qcept Technologies Inc. today announced that it has established an applications development relationship with a leading semiconductor capital equipment manufacturer to jointly apply Qcept's ChemetriQ non-visual defect (NVD) inspection technology for improving semiconductor processes, including wet cleans and surface preparation.
As part of this strategic relationship, the customer will purchase Qcept's latest-generation ChemetriQ 5000 NVD inspection system, which is planned to be shipped and installed at the customer site during the second quarter of 2011. The equipment manufacturer previously worked with Qcept, utilizing the results from a ChemetriQ inspection tool to help optimize product designs and processes. The result of this work was instrumental in leading to the decision to expand the business relationship through the purchase of the ChemetriQ system.
"Leading semiconductor equipment suppliers are constantly pushing the envelope to optimize their processes in order to meet their customers' ever-more-demanding production requirements. For wafer cleaning and surface preparation in particular, emerging process challenges at the leading edge require innovative methods to detect and reduce the effects of NVDs to ensure tighter process control," stated Bret Bergman, CEO of Qcept Technologies. "We are pleased that this leading equipment supplier has chosen to work with Qcept to optimize its cleaning processes with NVD inspection. Adoption of our ChemetriQ 5000 system continues to grow worldwide across the semiconductor ecosystem, including leading-edge device manufacturers and process equipment suppliers alike."
At 3X-and-smaller design nodes, improvements in semiconductor device performance are being driven as much by new materials and device structures as by traditional lithographic shrinks. These new materials and structures require extremely precise control of wafer cleaning and surface preparation—making these processes increasingly critical components of device yield. With wafer cleaning and surface preparation the most repeated steps in the fab—up to 100 times per wafer—there are many opportunities for a sub-optimal cleaning process to cause significant yield loss at these advanced design nodes.
