News Article
Research moves 3D IC closer
NANIUM and 3D Systems Packaging Research Centre join forces to enable Chip-Last commercialization
NANIUM signed an agreement to become a Supply Chain Member of the 3D Systems Packaging Research Center at the Georgia Institute of Technology (GT PRC) Embedded MEMS, Actives and Passives (EMAP) Industry Research Consortium. The EMAP consortium is a highly successful industry collaboration program that includes companies from around the world. As a Supply Chain Member in the EMAP consortium, NANIUM will contribute to the program serving in a Package Integrator capacity for the new technology.
The agreement is the foundation of the partnership, and the co-operation between the GT PRC, the largest academic research center in the field of semiconductor packaging, and NANIUM, the largest OSAT (Outsourced Semiconductor Assembly and Test) in Europe, is another excellent example of the growing global industry collaborations, in which GT PRC discovers new technologies and transfers them, as well as interdisciplinary educated engineers to industry, providing a path for commercialization of System-on-Package (SOP) based technologies, bridging the so-called "Valley of Death" between university research and commercialization.
NANIUM, as one of the providers of fan-out WLP (Wafer Level Packaging) solutions for single die and System-in-Package (SIP) currently utilizes Chip-First embedding in a reconstituted wafer approach. The incorporation of the EMAP Chip-Last embedding advancements will allow the extension of NANIUM's fan-out technology portfolio to SIP solutions for new applications and markets, including Interposers. This is expanding NANIUM offerings, which can benefit from Chip-Last over Chip-First approaches.
