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News Article

Rudolph order boost TSV uptake

Rudolph Technologies has announced that it has shipped its Wafer Scanner 3880 3D Inspection System, multiple NSX  Macro Defect Inspection Systems and its Discover Yield Management Software Suite to a leading semiconductor manufacturer for use in developing through silicon via (TSV) based processes for advanced 3D IC integration. In addition to speed and accuracy, the systems' flexibility to handle a wide range of applications was a key factor in the selection.

"We continue to see aggressive development efforts among our leading customers in the development of advanced 3D integration technologies using TSVs, micro bumps and complex back-end stacking and packaging processes," said Reza Asgari, Rudolph's Wafer Scanner product manager. "Although it is clear that 3D integration will come, the details of its implementation for many applications are still being developed. The solution set from Rudolph provides maximum flexibility in accommodating this very dynamic environment as we move from development to high-volume manufacturing."

For both standard and flip chip wafers, the Wafer Scanner Inspection System provides superior yield management for 3D/2D bump and RDL metrology, bump and RDL defect and macro defect inspection throughout post-fab processes. Utilizing Rudolph's patented Laser Triangulation Technology, the Wafer Scanner System enables 3D inspection of bumps and RDL of different sizes at high speed. A new, optional ultra-high resolution sensor enables inspection of micro bumps and RDL heights of as low as one micron.

The NSX Inspection System family is the market leader for automated macro defect inspection in advanced packaging applications. In addition to the WaferScanner 3880, the new NSX 320 System offers specific inspection solutions for processes using TSVs to connect multiple die in a single package; while continuing to serve critical metrology and inspection needs for via dimensions, die to wafer alignment, X and Z direction edge trimming metrology, wafer-to-wafer alignment during bonding/back-grinding/thinning processes, and sawn wafers on film frames.
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