News Article
Intel enters Teraflop era
At SC11, Intel Corporation revealed details about the company's teraflop processing chip with the first presentation of the first silicon of "Knights Corner" co-processor showed that Intel architecture is capable of delivering more than 1 TFLOPs of double precision floating point performance (as measured by the Double-precision, General Matrix-Matrix multiplication benchmark -- DGEMM*). This was the first demonstration of a single processing chip capable of achieving such a performance level.
"Intel first demonstrated a Teraflop supercomputer utilizing 9,680 Intel Pentium Pro® Processors in 1997 as part of Sandia Lab's "ASCI RED" system," Hazra said. "Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history."
"Knights Corner," the first commercial Intel MIC architecture product, will be manufactured using Intel's latest 3-D Tri-Gate 22nm transistor process and will feature more than 50 cores. When available, Intel MIC products will offer both high performance from an architecture specifically designed to process highly parallel workloads, and compatibility with existing x86 programming model and tools.
Hazra said that the "Knights Corner" co-processor is very unique as, unlike traditional accelerators, it is fully accessible and programmable like fully functional HPC compute node, visible to applications as though it was a computer that runs its own Linux*-based operating system independent of the host OS.
As previously announced at the International Supercomputing Conference 2011 in Hamburg, Germany, Intel's goal is to deliver Exascale-level performance by 2018 (which is more than 100 times faster performance than is currently available) while only requiring two times the power usage of the current top supercomputer. Fundamental to achieving that goal is working closely with the HPC community, and today Hazra announced several new initiatives that will help to achieve that goal.
Intel and the Barcelona Supercomputing Center (BSC) have signed a multi-year agreement to create the Exascale Laboratory in Barcelona, Intel's fourth European Exascale R&D lab that joins existing sites in Paris, Juelich (Germany) and Lueven (Belgium). This new laboratory will focus on scalability issues in the programming and runtime systems of Exascale supercomputers.
Additionally, the Science and Technology Facilities Council (STFC) and Intel have signed a memorandum of understanding to develop and test technology that will be required to power the supercomputers of tomorrow. Under this initial agreement, STFC's computational scientists at its Daresbury Laboratory in England and Intel will work together to test and evaluate Intel's current and future hardware with leading software applications to ensure that scientists are ready to exploit Intel's supercomputer systems of the future.
