News Article
Tegal Continues Discussions For Patent Portfolio
Tegal Corporation has announced renewed efforts to make available the balance of its semiconductor process-related intellectual property portfolio. The remaining portfolio consists of thin film structures and process technology pertaining to copper barrier and low-k dielectric technology.
"Tegal's patented process solution addresses the removal of volatile molecules from the porous material prior to the deposition of a capping layer."
On December 30, 2011, Tegal announced that it had sold over thirty patents from Lots 1-3 of its Nano Layer Deposition (NLD) Patent Portfolio to multiple bidders for an aggregate consideration of approximately $4 million. Interest in Lots 1-3 had come primarily from capital equipment manufacturers, whereas ongoing discussions regarding the sale of Lot 4 of the NLD Patent Portfolio is primarily with IC device manufacturers and intellectual property aggregators.
"As low-k dielectrics become more porous, methods for sealing these open pores will become increasingly important for integration with subsequent processing," says Robert Ditizio, Tegal's Chief Technologist. "Tegal's patented process solution addresses the removal of volatile molecules from the porous material prior to the deposition of a capping layer."
Integrated processes of this type will be a necessary part of any integrated processing scheme for advanced low-k dielectrics that utilize porous low-k films. In addition, Tegal's portfolio contains solutions for composite barrier layers and adhesion layers for copper metallization strategies that have become increasingly relevant for ALD, NLD, and CVD deposition of multiple layers, including adhesion layers, barrier layers, and seed layers, whether these seed layers are Cu, Ru or Mo. Alternatives to currently employed PVD deposition methods with ALD, and derivatives of ALD, are being investigated to meet the demands for higher aspect ratios, improved step coverage, and control of copper diffusion. These requirements are placing increasing demands on the precise control of advanced metallization schemes, particularly at the lower metallization layers on advanced CMOS devices. To overcome the step coverage limitations with PVD techniques, developers are relying on ALD and NLD methods for constructing the barrier, adhesion, and seed layers with atomic layer precision and control of thickness, uniformity, and stoichiometry.
The availability of Tegal's patents provides a unique opportunity for IC developers and IP aggregators to expand their patent portfolio with potentially fundamental patents for advanced metallization schemes, particularly suitable for the transition from PVD to ALD and other layer-by-layer techniques.
