News Article
SEMATECH Revolutionising Silicon Semiconductor CMOS Technologies
The R & D institute has developed extending advanced memory and logic processes for high mobility channel CMOS devices, FinFETs, RRAMs and more
Today nearly all electronic devices are built on CMOS technology. For over half a century, silicon-based materials have been the basic layers used in the manufacturing of CMOS transistors.
However, silicon and materials derived from it, such as insulators and contact metals are reaching their limits, as the industry looks to lower power dissipation in CMOS devices and as scaling approaches the physical limits of silicon transistors.
To tackle this, SEMATECH researchers have developed innovative materials and new transistor structures to address key aspects of transistor performance, power, and cost. The scientists described their results in nine papers at the International VLSI Technology, System and Applications Symposium (VLSI-TSA) .
"Through intense research and development efforts, SEMATECH is developing manufacturable solutions and practical implementation approaches for innovative materials in future transistor structures," says Raj Jammy, vice president of emerging technologies. "The research that was presented at VLSI TSA demonstrates SEMATECH's leadership in developing new materials, processes and concepts that will pave the way for emerging technologies."
One potentially industry-changing technology, is a direct metal bonding interconnect approach. For 2.5D and 3D integration to reach its full potential, chip-to-interposer and chip-to-chip interfaces have to support a very large number of power and signal connections. Currently, most solder-based interconnect schemes will not scale sufficiently due to mechanical, electrical, thermal, and reliability limitations.
SEMATECH's copper-to-copper direct bonding (CuDB) technology is a promising new technology to aggressively scale chip-to-chip interconnects and keep pace with advances in TSV. There are still however technical and economic hurdles in moving toward high-volume manufacturing of CuDB interconnects.
Regarding silicon channel devices, SEMATECH evaluated stress-induced leakage current (SILC) in full gate-last (FGL) high-k/metal gate devices. They found that a high quality interlayer during gate stack formation was critical to improving FGL device performance and reliability.
The researchers also modelled positive bias temperature instability (PBTI) degradation in zirconium-doped HfO2 gate stacks by considering fast and slow electron trapping processes. PBTI was found to improve when the fast trapping component was suppressed.
SEMATECH also looked into a number of approaches to non-planar devices. With FinFET Vt chips, both the performance and the electrical properties of the gate stack were improved by implanting aluminium into the structure. SEMATECH says this represents progress towards realising multi threshold voltage FinFET device architectures for the 14 nm node and beyond.
Also, threshold voltage can be effectively modulated with doping in ~25 nm wide fins in high-k/midgap metal gate SOI FinFETs. For sub-10 nm fin widths, however, the active dopant atoms must be precisely placed inside the fins, which cannot be done using ion implantation. A conformal doping technique with perfect dose control, such as monolayer doping, may be the answer for future planar and non-planar devices.
The scientists also found that by using a fixed fin-to-height ratio in double-gated (DG) FinFETS, and optimising the process, parasitic capacitance can be reduced and be made comparable to planar FETs. It is crucial, however, to control the fin width and height in the DG FinFETs, to prevent the parasitic capacitance uniformity from degrading.
Other investigations focussed on the impact of source/drain (S/D) activation anneal on GAA pFETs. Low temperature pFETs were fabricated and benchmarked against devices with a S/D activation anneal. When S/D is implanted before the gate spacer, the un-annealed devices exhibited higher peak transconductance and drain current but had a higher off-current than their annealed counterparts.
In terms of advanced non-volatile memory, RRAM switching performance of up to 1x108 cycles at low power and a hundred times reduction of the high-resistance-state current was achieved by identification and utilisation of key parameters for establishing superior control of the RRAM conductive filament formation.
