SMIC Takes A New Approach to Endorsing Its Semiconductor System on Chips
Semiconductor Manufacturing International Corporation (SMIC) is
using Mentor Graphics' Calibre
PERC circuit reliability verification solution as part of its latest
electrostatic discharge (ESD) protection design methodology.
This new approach helps ensure whole chip ESD protection for large, complex SoCs, including all I/Os, embedded IP blocks from SMIC or third-party sources, and eFuse embedded memory.
SMIC adopted the Calibre PERC solution because it can combine schematic and physical layout criteria and measurements to perform advanced reliability checks that until now were primarily done manually.
"New applications and use models create more difficult ESD protection challenges for designers due to increasing breakdown voltage variability, and a greater number of vulnerable circuit nodes at the interfaces between voltage domains in low power designs," says Tianshen Tang, vice president of design service at SMIC.
"We offer a multi-pronged approach that includes robust ESD protection in our IP libraries, running circuit checks for our customers using Calibre PERC with SMIC rule decks, and consulting services to assist customers with their specific ESD performance and reliability needs. We will also issue Calibre PERC design kits for our customers by mid-year so they can define and run their own checks," he explains.
SMIC is using the Calibre PERC platform's Logic-Driven-Layout analysis capability to ensure that all designs, including SMIC IP libraries and customer designs, conform to SMIC's ESD design rules
The integrated ESD protection techniques have a common ESD ground bus for the entire I/O ring to ensure safe discharge and a cross-voltage domain and analogue-digital interface protection. With fast trigger protection, the devices have an enhanced design margin and low leakage protection circuits and high latch-up immunity. They also feature local ESD protection for IP cores and eFuse memories.
The Calibre PERC product detects violations and provides designers with a holistic environment for debugging circuit reliability problems with an integrated view of circuit connectivity, topology, physical layout and design rules.
"Designers are realising that regardless of the process
dimension they are targeting, circuit reliability checking is a growing issue
that requires much more sophisticated automation than in the past," says
Michael Buehler-Garcia, senior director of marketing for Calibre Design
Solutions at Mentor Graphics.
"The impact on yield and long-term reliability grows at each successive node, so designers should plan to make advanced reliability checking an integral and permanent addition to their design flows."
