+44 (0)24 7671 8970
More publications     •     Advertise with us     •     Contact us
*/
News Article

GLOBALFOUNDRIES Enables 20nm Silicon Double Patterning

News
Extensions and validation of analogue/mixed-signal flow at 28nm, now provides advanced support for 20nm qualification


At this week's Design Automation Conference (DAC) in San Francisco, California, GLOBALFOUNDRIES is to demonstrate an enhanced silicon-validated design flow for its 28nm Super Low Power (SLP) technology with Gate First High-k Metal Gate (HKMG).


The flow is claimed to provide complete front-to-back support for advanced analogue/mixed-signal (AMS) design using the industry's latest design automation technology.


What's more, the company will reveal jointly developed design flows with its EDA partners in certifying both analogue and digital "double patterning aware" flows for its 20nm process, with silicon validation expected in early 2013 at that technology node.


GLOBALFOUNDRIES says now its customers can produce signoff-ready 28nm digital and analogue designs using one of the industry's most advanced set of design tools, tool scripts, and methodologies.


The company's tight collaboration with the design tool and IP ecosystem also accelerates its ability to develop working flows for advanced nodes such as 20nm, providing advantages in gate density, performance, and lower power to customers.


"Our approach to early collaborative development work with our design enablement partners continues to keep us at the leading-edge of process technology and deliver proven and reliable solutions to customers," says Mojy Chian, senior vice president of design enablement at GLOBALFOUNDRIES.


"At 28nm, and even more so at 20nm, process technology and design tool flows must be in lock step in order to address the significant design-to-manufacturing challenges that arise. We work closely with our partners to identify innovative approaches to deal with challenges such as timing variations for digital ICs and layout dependent effects in custom chips. These most recent flows demonstrate the strength of our model, as well as the innovation and expertise required to offer foundry solutions at this level."


The GLOBALFOUNDRIES 28nm AMS production flow is a Mixed Vendor Flow supporting tools from multiple vendors, including Cadence Design Systems for layout with Virtuoso technology; Synopsys and Cadence for parasitic extraction; and Mentor Graphics for physical verification.


The flow is an integrated mixed-signal flow which is claimed to provide complete support for a digital implementation module based on the Encounter Digital Implementation System from Cadence. This approach enables the integration of analogue IP into a digital SOC design using production standard cells.


Furthermore, the flow now includes inductor synthesis and extraction support from specialised EDA suppliers Lorentz Solutions, Helic and Integrand Software. The flow has also been augmented with support for fast variation-aware analysis using the Variation Designer platform from Solido Design Automation, and EM/IR analysis using the Totem software platform from Apache Design. A DRC waiver flow is available from Mentor Graphics' Calibre tool suite.


The 28nm AMS Production Design flow is fully validated with silicon results from an analogue design with validated functionality from 300MHZ up to 3Ghz. Silicon validation includes clock duty cycle, peak-to-peak period jitter and operating current for key analogue blocks.


The 28nm flow option supports DRC+, the company's silicon-validated solution that goes beyond standard Design Rule Checking (DRC) and uses two-dimensional shape-based pattern-matching to enable up to a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy.


The flows are fully integrated with the PDK and maintained and supported by GLOBALFOUNDRIES.


At 20nm, GLOBALFOUNDRIES and its design enablement partners have focused on critical new manufacturability issues, including the limits of traditional lithography and the need for even more robust DFM techniques. A key requirement is double patterning "“ the splitting of metal layers into two masks "“a technique that is best supported in customers' design flows.


The firm has developed two fully executable 20nm RTL2GDSII flows for its 20nm process, one based on the Galaxy suite of tools from Synopsys and the other based on the Cadence Encounter platform. Both flows are being silicon validated by designing a complex double patterned test chip. The flows support synthesis, colour aware place-and-route, parasitic extraction, STA and physical verification. Mentor Graphics Calibre is used for decomposition and physical verification.


The flows support the use of double patterning at each step of the design process, including "˜double patterning aware' placement, routing, optimization, extraction, and physical verification. The double pattering support also allows the customer to choose to decompose portions of the different mask themselves or to use an automated approach for decomposing the masks and assigning colours.
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: