Cadence & TSMC Unite To Develop Silicon 3D-IC Chip Technology
3D-ICs require co-design, analysis and verification of
heterogeneous chips and silicon carriers.
Now, TSMC and Cadence have worked together to create and integrate features to support this new type of design. This has culminated in the test-chip tapeout of TSMC's first heterogeneous CoWoS (Chip-on-Wafer-on-Substrate) vehicle.
Cadence's 3D-IC technology enables multi-chip co-design between digital, custom and package environments incorporating through-silicon vias (TSVs) on both chips and silicon carriers. It supports micro-bump alignment, placement, routing and design for test. It includes key 3D-IC design IP, such as a Wide IO controller and PHY to support Wide IO memories. Test modules were created using the Cadence Encounter RTL-to-GDSII flow, Virtuoso custom/analogue flow, and Allegro system-in-package solutions.
"In 2012 3D-IC became a viable option for real-world chip design," says John Murphy, group director, Strategic Alliances at Cadence. "For 10 years, Cadence has invested in SiP (System in Package) and 3D-IC design capabilities. Now we can share this knowledge with designers to bring this versatile technology to market."
Cadence 3D-IC technology helps enable device designs
that will be incorporated into TSMC's recently introduced CoWoS process.
CoWoS is an integrated process technology that bonds multiple silicon chips in a single device to reduce power, improve system performance and reduce form factor.
"Big leaps in electronic design don't happen without
strong collaboration, and our partnership with Cadence in CoWoS design is a
good example," notes Suk Lee, TSMC senior director, Design Infrastructure
Marketing Division. "For 3D-IC design ecosystem readiness, Cadence played an
important role in the development of design technology and the necessary IP."
