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Novel Wafer-Scale CMOS Developments Boost X-Ray Imaging

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A highly innovative high-resolution wafer-scale digital image
sensor that targets medical imaging applications has been developed at the Science
and Technology Facilities Council's (STFC) Rutherford Appleton Laboratory
(RAL).

One of the key aspects in the development of this CMOS imaging
sensor by the STFC's CMOS Sensor Design Group, was the use of advanced analogue
tools from Tanner EDA, a leading provider of tools for the design, layout and
verification of analogue and mixed-signal integrated circuits (ICs). 

Measuring 120 x 145 mm and effectively using an entire 200 mm
silicon wafer in its production, the new image sensor is being manufactured by TowerJazz,
a global specialty semiconductor foundry, using its special CMOS sensor process
technology.

The primary target application for the new sensor is X-ray medical
imaging and more specifically mammography and digital tomosynthesis, the
advanced diagnostic technique used to generate 3D representations of patients
or other scanned objects. There is increasing interest in the use of
solid-state-based X-ray detection systems in the replacement of conventional
diagnostic imaging techniques. 

One of these technologies is CMOS sensor based imaging, which can
bring key advantages in terms of performance such as high resolution, high
dynamic range and low noise capabilities. In addition, it can offer significant
system cost advantages for X-ray imaging applications, although it can come
with an initial penalty in terms of design complexity in the actual development
of the CMOS sensor.

As no lens is used in CMOS-imaging-based X-ray applications, the
size of an image sensor has to match the size of the target area. While in some
medical imaging applications such as extra-oral panoramic dental imaging, a
sensor measuring 139 x 120 mm is usually adequate. However, this is not big
enough for most medical applications. For example, mammography applications
require a sensor that is approximately 290 x 240 mm in size, and even larger
for chest radiography. In other applications such as full body scanning for
security purposes, an even more extensive sensor area can be necessary.

The new STFC high-resolution and radiation-hard CMOS sensor has
been developed to meet these challenges. A unique feature of the device is that
it has sensing pixels right up to the edges on three sides of the imager. This
allows multiple sensors, manufactured on cost-effective 200 mm silicon wafers,
to be "˜butted' or "˜tiled' together in a 2 x 2 arrangement to form a significantly
larger imaging area and to meet the requirements for mammography applications.
Additionally, any 2 x N sensor arrangements are possible, thus making the
device ideal for applications that demand even larger area coverage, such as
chest imaging or security scans.

Conventional CMOS imagers have the required electronic circuitry
implemented on two sides of an imaging array to address the individual sensor
pixels. To achieve this three-side "˜buttable' design, the STFC CMOS Sensor
Design Group developed some innovative electronic circuitry IP (Intellectual
Property) to implement the necessary pixel readout and row-addressing driver
functions on just one edge of each sensor, with extra circuitry embedded in the
actual pixel array, while maintaining a high degree of image quality.

The full-custom-design sensor, which offers a focal plane of 139.2
x 120 mm, has 6.7 million (2800 x 2400) pixels on a 50µm pitch, 32 analogue
outputs and also features low noise, a high dynamic range and a programmable region-of-interest
readout. Each pixel is constructed from a basic three-transistor (3T) base with
a low-noise partially pinned photodiode, offering "˜charge-binning' capability
to deliver its high signal-to-noise characteristics.

This means the sensor can offer a very high frame rate of 40 frames
per second at full resolution and "˜binned' images can be read at an
increasingly faster rate. The high frame rate makes the sensor ideal for
applications that demand fast acquisition of multiple images such as in digital
tomosynthesis, which is receiving increasing interest in the medical field.

The STFC CMOS Sensor Design Group worked with Tanner EDA and its
exclusive representative in Europe, EDA Solutions, to use the Tanner tools to
develop the innovative pixel-addressing IP, which was almost entirely analogue
circuitry with only a small amount of on-chip digital logic. 

In particular, the STFC design group used Tanner Tools Pro, in
conjunction with Tanner's HiPer Verify tool. Tanner Tools Pro is a
comprehensive software suite for the design, layout and verification of analogue,
mixed-signal, RF and MEMS ICs. The tool suite comprises fully integrated
front-end and back-end tools including schematic capture, circuit simulation,
waveform probing, physical layout and verification. Tanner's HiPer Verify is a
comprehensive and affordable solution for analogue and mixed-signal IC design
rule checking (DRC) and hierarchical netlist extraction.

The STFC design group also worked closely with TowerJazz for the
manufacture of the sensor, which is implemented in a 180/350nm dual-gate CMOS
Image Sensor (CIS) process technology on 200mm wafers. TowerJazz's CIS technology
process enables the customisation of pixels, according to project needs for
many digital imaging applications, offering excellent dark current, low noise
and dynamic range performance characteristics.

"The STFC works closely with its partners, such as Tanner EDA and
TowerJazz, to develop innovative solutions that meet highly demanding
requirements in a range of scientific and industrial applications," said Dr.
Renato Turchetta, CMOS Sensor Design Group Leader at the Science and Technology
Facilities Council's Rutherford Appleton Laboratory.

"The complete set of Tanner EDA tools was extremely well suited
for the design of this sensor with its complex analogue architecture. This, in
conjunction with the high yield of the TowerJazz CMOS Image Sensor process
technology, was instrumental in achieving a first-right-time design with no
prerequisite for any initial prototype design."


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