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News Article

How To Push Out Adoption of 3D TSV



A considerable amount of work has been undertaken in the last several years to develop 3D TSV technology for high volume manufacturing. But challenges are slowing the commercialisation of the technology despite the strong desire to use it.

A new study, "3D TSV Markets: Applications, Issues, and Alternatives", by Tech Search contains a realistic five year market forecast for PoP, 2.5D, and 3D TSV applications in units and wafers.

While the drivers for 3D ICs remain constant, the time line for its adoption continues to shift. Several technical challenges and infrastructure issues such as business logistics are delaying the full commercialisation of TSV technology for 3D ICs.

There are a number of issues which are hampering the adoption.

One is EDA tool availability including the ability to use thermally aware tools and the ability to communicate between tools. Manufacturing yield in key process steps such as debonding during wafer thinning is another factor.

Thermal dissipation, cooling methods, test methodology and infrastructure-related issues, including logistic supply chain handoff are also a major concern. Finally, the reliability of data for a broad range of applications and device cost compared to the alternatives are an issue.

Once these 3D TSV technical challenges are resolved and the technology becomes cost-effective, business challenges will remain until the industry settles on a model.

As the boundary between foundry and assembly processes continues to blur, there will be a struggle to determine which organisations can best meet the customer's needs for assembly and test.

Any one of these issues has the potential to limit full 3D TSV implementation, and these challenges are driving many companies to seek alternative packaging and assembly solutions until these issues can be sorted out.

 


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