Microsemi Buffers Improve Communications Timing
Microsemi Corporation has expanded its communications timing portfolio with its first family of clock distribution differential fan-out buffers.
The 28-part family of buffers supports clock rates of up to 750 megahertz, low voltage differential signalling and multiple fan-out ratios.
Internal and external terminations for inputs eliminate the need for external peripheral components.
The ultra-low additive output jitter also leaves the majority of the jitter budget to the high speed transceivers. The combination of these features results in lower bill-of-material (BOM) costs.
The new clock buffers devices are synergistic with Microsemi's broad timing portfolio and, when used together, provide customers improved board performance and complete timing solutions.
"Broadening our current timing and synchronisation offering with our new buffer family allows us to offer customers a complementary building block for clock generation and synthesis products," says Maamoun Seido, vice president and business unit manager of Microsemi's timing products.
"Communications is a key area of focus for Microsemi. With our investments in this area, including the acquisition of Maxim's timing, synthesis and synchronisation business earlier this year, we now have the roadmaps and resources in place to capitalise on growing opportunities in this market segment."
Microsemi says its buffers deliver the industry's lowest additive jitter combined with best power supply noise rejection performance.
This preserves signal integrity by adding ultra-low jitter and filtering noise from power supplies, resulting in better performance while simplifying engineering board design efforts.
Also, the flexible I/O structure and internal on chip input terminations eliminate the need for external components.
Microsemi's new fan-out buffers are available in production quantities now.
