Freescale gains Synopsys' verification IP
Synopsys has announced advancements in its longstanding verification collaboration with Freescale Semiconductor.
With a focus on addressing the increasing complexities of system-on-chip (SoC) verification, Freescale teams are leveraging Synopsys' innovations in verification IP (VIP), simulation performance, debug technology and methodology development.
This collaboration is targeted to achieve better schedule predictability and lower overall verification costs for Freescale's complex SoCs.
"Over the last few years, our designs have led a very aggressive roadmap of SoC platforms with considerable verification challenges. Now, with the increasing use of standards-based IPs, verification challenges shift to finding the fastest and most effective way to validate the integration of complex protocols with our differentiated SoC content, while boosting debug and simulation performance," says Ken Hansen , vice president and chief technology officer at Freescale Semiconductor. "Synopsys' simulation and VIP portfolio provides our teams with increased performance, UVM support, and advanced debug capabilities."
"This strategic collaboration with Freescale builds on the successful engagement we have had for more than a decade," adds Manoj Gandhi , senior vice president and general manager of the Synopsys Verification Group. "We appreciate our mutual collaboration and look forward to continuing to deliver next-generation verification technology that addresses Freescale's SoC verification challenges."
