One clock, many chips
As heterogeneous computing grows, precise timing is becoming
increasingly critical. SiTime's Chorus 2 simplifies synchronization across AI,
HPC and networking platforms.
AI training clusters, smart factory vision systems and SmartNIC-based networking platforms are driving a shift in electronic system design. Rather than relying on a single processor, today's architectures combine CPUs, GPUs, ASICs and FPGAs, each operating at different frequencies and with unique timing requirements. While this heterogeneous approach delivers greater performance, it also introduces a significant challenge: maintaining precise synchronization across every device.
Traditionally, designers assigned a dedicated timing device to each processor or subsystem. Although effective, this approach increases board space, power consumption and design complexity while making system-wide synchronization increasingly difficult as data rates continue to rise.
SiTime addresses this challenge with its Chorus 2 programmable clock generator, a wide-frequency-range timing solution that consolidates multiple clock sources into a single device. By replacing up to eight or twelve discrete oscillators or clock signals, Chorus 2 simplifies board design while improving performance, reducing power consumption and enhancing overall system reliability.
Designed for AI servers, high-performance computing (HPC), datacentre networking, industrial automation and advanced consumer electronics, Chorus 2 provides the flexibility needed for modern multi-chip architectures. Each output can operate at a different frequency, with up to 20 programmable configurations available to support diverse system requirements. Unused outputs can also be disabled, reducing both power consumption and electrical noise.
The device is particularly suited to high-performance networking applications requiring PCI Express (PCIe) Gen7 support and low-jitter SerDes clocks. In AI servers and GPU baseboards, where multiple PCIe switches and retimer ASICs require independent clock sources, Chorus 2 consolidates these timing requirements into a single programmable device while maintaining precise synchronization across the platform. Pin-to-pin compatibility with competing solutions also enables straightforward upgrades within existing designs.
Key performance improvements include:
- PCIe Gen7-compliant clock generation
- Less than 110 fs jitter at 156.25 MHz, delivering up to twice the jitter performance of competing solutions
- Up to 2.5 times lower output-to-output skew
- Four independent spread-spectrum clock outputs
- Flexible frequency generation using fractional dividers
- Support for up to 20 one-time programmable (OTP) configurations
As system architectures continue to evolve, timing is becoming a critical design discipline rather than a supporting function. By combining multiple timing functions within a single programmable device, Chorus 2 reduces component count, frees valuable PCB space and simplifies system design while delivering the precision required for next-generation AI, networking and industrial platforms.
The Chorus 2 clock generator is now in volume production, with samples available immediately in both 12-output (SiT95272) and 8-output (SiT95278) QFN package options, providing designers with a scalable timing platform for increasingly complex heterogeneous computing systems.
