+44 (0)24 7671 8970
More publications     •     Advertise with us     •     Contact us
*/
News Article

ISMT qualifies ultra-low-k MSQ

International SEMATECH (ISMT) engineers have qualified a porous, ultra low-k material for dual damascene copper processing at 130nm feature sizes, on 300mm wafers, using 193nm lithography.
International SEMATECH (ISMT) engineers have qualified a porous, ultra low-k material for dual damascene copper processing at 130nm feature sizes, on 300mm wafers, using 193nm lithography.

The material is a porous methylsilsesquioxane (MSQ) film consisting of silicon-oxygen and hydrocarbons with a physical structure similar to meringue. MSQ has a dielectric constant (k) of about 2.5, compared with the low-k materials now in use whose k-values range from 2.65 to 3.0. The ultimate low-k is vacuum (k=1).

ISMT technologists believe that their achievement with the new material means that ultra low-k materials - which allow extremely thin copper lines to be placed very close together on a chip without short-circuiting or leaking current - could be ready for use in commercial manufacturing within two to five years.

"This milestone enables us to have a baseline process for evaluating advanced materials and new technologies," says Josh Wolf, ISMT engineering manager. "And it gives our member companies the ability to evaluate ultra low-k materials using current manufacturing processes to meet the requirements of the 65nm technology node."

Throughout the industry, development of low-k materials has lagged the pace of other areas of semiconductor R&D, chiefly because low-k compounds must generally be porous. These materials also must serve as good insulators, while remaining strong enough to withstand the chemical and mechanical rigours of chip processing. Teams of ISMT engineers and assignees, managed by Wolf, Gregory Smith and Klaus Pfeifer, met these challenges by adjusting several manufacturing processes to work with the MSQ material.

Porous MSQ presented several process challenges involving carbon depletion of the film, structural weakness and susceptibility to chemical attack. To compensate, the ISMT engineers modified several steps in the dual damascene process.

To handle one of the key stages that can damage low-k films - chemical-mechanical planarisation (CMP) – the rotation speed and downforce of the polishing pad was controlled and the chemical slurry polishing suspension was optimised.

Further, advanced etch, ash and cleans processes were developed with enhanced selectivities and uniformities to use with very thin etch stops and capping layers. This lowers and preserves the overall dielectric constant of the entire structure using the MSQ material.

Wolf reports that the achievement took seven months of work and involved four projects in ISMT's Interconnect division. The Interconnect division concentrates on evaluating and qualifying low-k materials for baseline processes in dual damascene manufacturing, and advancing barrier, seed and metallisation technologies for use with copper and low-k interconnects.

×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in: