Intel produces 65nm SRAM
This new process combines higher-performance and lower-power transistors, a second-generation version of Intel’s strained silicon transistors, high-speed copper interconnects and a low-k dielectric material.
"This accomplishment puts Intel’s 65nm technology on a fast track to extend our 15 year record of ramping production on a new process generation every two years," comments Dr Sunlin Chou, senior vice-president and general manager of Intel’s Technology and Manufacturing group. "In fact, only 20 months have elapsed since we disclosed achievement of fully functional SRAMs on our 90nm process, which is now ramping."
The 65nm process will feature transistors measuring only 35nm in gate length. The transistors in Intel’s Pentium 4 processors currently measure 50nm. The strained silicon technology provides higher drive current, increasing the speed of the transistors with only a 2% increase in manufacturing cost, Intel says. The process also integrates eight copper interconnect layers with a low-k dielectric material to increase signal speeds and reduce power consumption.
The 4Mbit SRAM chips used to test the process have a 0.57micron2 cell size (1.0micron2 on the 90nm process). Small SRAM cells allow for the integration of larger caches in processors, which increase performance. The SRAM cells have robust operating characteristics, with a solid noise margin indicating very efficient on/off switching properties. The noise peformance of the SRAM cells give adequate performance with operating voltages down to 0.7V. Each SRAM memory cell has six transistors. The process can fit 10mn transistors into 1mm2.
The 65nm semiconductor devices were manufactured at Intel's 300mm development fab (D1D) in Hillsboro, Oregon, where the process was developed. The process will now be ramped to high-volume at D1D before transfer to other facilities in 2005. D1D is Intel’s fourth 300mm facility and boasts the company’s largest individual cleanroom that covers a floor area of 16,350m2.
Intel’s in-house mask making team produced advanced masks that extended 193nm lithography to the 65nm process. The company expects to reuse the 193nm and 248nm lithography equipment currently used on its 90nm process, as well as adding some upgraded 193nm tools. This lowers implementation costs and ensures a mature tool set for the ramp up.
The mask sets use both optical proximity correction (OPC) and phase-shift (PSM) techniques. The company uses a phase-shift technique that etches into the glass substrate, providing 180 degree phase-shifts between adjacent lines to sharpen the image. Also the circuit design rules are constructed to improve yield rates.
The company is currently developing extreme ultraviolet lithography for possible use on 32nm processes (due 2010).
Intel’s spokesman, Mark Bohr, Senior Fellow and director of process architecture and integration, took time at the press conference to defend the advantages of integrated device manufacturing. Among the benefits, he says, are the ability to control critical components such as silicon processing, mask making and circuit design along with the interactions between them.
