Sematech creates high-k baseline
The high-k material is hafnium silicide (HfSiOx), which ISMT technologists have been working with for more than two years.
Project manager Byoung Hun Lee says that the new baseline process has been used to build a functional high-k/metal gate device with several good characteristics, including:
* Symmetrical threshold voltages (Vth) for NMOS and PMOS channels of approximately 0.82V and 0.85V respectively, located at the mid-gap region
* No reaction between the polysilicon capping layer and the underlying hafnium-silicate
* NMOS drive current performance of 1.02mA/micron (Ion) and 10nA/micron (Ioff) at 1V overdrive (at Tinv =1.85nm and Lpoly ~70nm)
* No evidence of Fermi-level pinning - a persistent industry technical issue
The baseline process was developed by ISMT's Front End Processes (FEP) division in co-operation with the consortium's Advanced Technology Development facility.
The 2003 edition of the International Technology Roadmap for Semiconductors targets high-k/metal gate high-performance devices for production availability at the 65nm node in 2007.
The 85nm baseline process comes from a previous high-k milestone that ISMT reached in January. Then, consortium engineers pioneered an etch process allowing the removal of high-k film from a wafer surface without damaging the underlying silicon. The new process has eased the way to implementation of advanced gate stacks, which are critical to the continued development of IC transistors.
"With these achievements, we're prepared to develop a manufacturable high-k/metal gate solution for our member companies - which in turn will benefit the entire industry," says Larry Larson, FEP associate director.