IEDM contributions

Infineon

Germany’s Infineon highlighted its research and development activities with several presentations. The papers present recent developments on DRAMs, organic semiconductors and memories and biochemical sensors. The company is also keen to identify key technologies for "Ambient Intelligence" applications where standalone electronic appliances and devices disappear into the environment of the individual.

Organic non-volatile memory

In one paper, Infineon describes cell concepts and requirements for non-volatile memories using organic materials. Memory cells built in this technology already demonstrate promising reliability data - for the first time, says Infineon, retention data of more than a year are shown for an organic memory material exhibiting conductance switching. Further investigations have shown potential for scaling the material down to feature sizes of less than 20nm.

Molecular weight lifting

Infineon has also developed a new biochemical sensor principle based on interface biochemistry using a bulk acoustic wave oscillator for mass sensing. This replaces traditional complex and expensive optical detection systems with a low-cost and sensitive electronic sensor. A record resolution of more than 0.1ng/micron2 has already been demonstrated. The system could be used in a wide range of pharmaceutical or health care applications like protein body/anti-body or DNA hybridisation detection.

Trench integration

On DRAM trench integration, Infineon has co-developed with Dow (Europe and Belgium) a thermally stable organic polymer. The new approach uses a modified version of an organic spin-on polymer for gap fill processes that has good planarisation properties and temperature stability beyond 450C. The 256M DDR DRAM chips fabricated on 140nm ground rules show high yields. Infineon believes the integration scheme is capable of extending DRAM trenches to generations below 70nm. Other Infineon papers cover organic thin film transistors (TFTs) and modelling of atomic layer deposition processes and atomic level (tight binding) transport modelling of silicon-on-insulator transistors.

SET to combine with CMOS

Texas Instruments and the Swiss Federal Institute of Technology of Lausanne detailed a way to use single electron transistors (SETs) to perform logic functions. SETs are one possibility for going beyond current semiconductor devices to dramatically reduce size and power consumption. The research indicates that a combination of SETs and standard CMOS transistors can provide enough gain and current drive to perform logic functions at a much smaller scale than will eventually be possible with CMOS alone. In an SET, one reaches the theoretical limit of electrons for computing applications by allowing the use of a single electron to represent a logic state.

"Looking out ten years and beyond, TI sees that the CMOS roadmap will need help to continue to deliver the predictable returns the industry has counted on for decades from Moore's Law," says Christoph Wasshuber, a Texas Instruments scientist and co-author of the IEDM paper. "It is starting to look viable for CMOS to continue to play a major role by providing a traditional system interface to millions of radically smaller, lower power, single electron transistors."

The researchers see general agreement that standard silicon CMOS should support scaling for the next 10-15 years using traditional field effect transistors (FETs) that use large numbers of electrons in operation. Cost effective advancement beyond that will require vastly different approaches in materials and architecture. Tightly packed FETs run into problems managing signal integrity and heat.

Simulations from the research show very encouraging results. The major SET obstacle of random background charges is also addressed in the paper. The scientists present a modulation technique that takes advantage of the periodic current voltage characteristic of SETs.

The next challenge for researchers is to manufacture reliably many SETs in a CMOS compatible process on silicon. The first application for SETs could be for memory and special applications in metrology, such as primary thermometers and super sensitive electrometers.

High-k proposal

On more tradition processes, TI has demonstrated the viability of a new high-k dielectric material - hafnium silicon oxynitride (HfSiON). Use of higher-k gate dielectrics can prevent the critical insulation in the transistor from becoming so thin that leakage currents reach unacceptable levels. TI's new work addresses concerns about HfSiON regarding thermal and electrical compatibility with standard CMOS processes, carrier mobility and threshold voltage stability.

"TI believes it has found an effective way of balancing the right material combinations to begin replacing the present silicon oxynitride layer with a Hf-based high-k dielectric in the next few technology generations," comments Hans Stork, senior vice president and director of silicon technology development. "We are seeing mobility that is 90% of the silicon dioxide universal mobility curve with dramatically lower leakage current without sacrificing reliability or adding significant cost to the CMOS process."

Integration of high-k gate dielectrics into future CMOS devices will be possible only if the dielectric is thermally stable during CMOS processing and electrically stable during normal operation. TI believes that the stability of its HfSiON is far superior to that of the HfO2 commonly investigated as a high-k gate dielectric.

45nm without high-k gate

AMD provided detail on its next-generation silicon-on-insulator (SOI) transistor design, while also providing new information on its successful use of SOI technologies in its current microprocessors. The 45nm node transistor uses fully depleted SOI (FDSOI), metal gates (nickel-silicide, rather than polysilicon) and a locally strained channel. A high-k gate dielectric is NOT used because of their negative effect on some aspects of transistor performance.

Self-assembled memory

IBM says that it is the first to successfully apply a novel "molecular self assembly" approach to aid conventional semiconductor processing. The nanotechnology technique is compatible with existing chip-making tools. This would avoid the high cost of tooling changes and the risks associated with major process changes.

The self-assembly technique uses polymer molecules to pattern critical device features in a memory device that are smaller, denser, more precise and more uniform than can be achieved using conventional methods like lithography.

The polymer patterns the formation of a dense silicon nanocrystal array that becomes the basis for a variant of conventional Flash memory. Nanocrystal memories are difficult to fabricate using conventional methods. Device processing, including self assembly, was performed on 200mm diameter silicon wafers.

IBM expects self-assembly techniques could be used in pilot phases three to five years from now.