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IMEC progresses high-k/metal gates

IMEC says that it has successfully demonstrated the use of high-k dielectrics and metal gates to values below 1nm. The European research centre believes that this level of electrical performance removes one of the industry's 'red brick walls' to advancing semiconductor technology. The research team used metal gates to overcome the problems imposed by the interaction between high-k materials with the commonly used polysilicon electrode.
IMEC says that it has successfully demonstrated the use of high-k dielectrics and metal gates to values below 1nm. The European research centre believes that this level of electrical performance removes one of the industry's 'red brick walls' to advancing semiconductor technology. The research team used metal gates to overcome the problems imposed by the interaction between high-k materials with the commonly used polysilicon electrode.

Using TiN or TaN gates and HfO2 as dielectric, aggressive scaling down to a 0.8nm equivalent-oxide thickness (EOT) was demonstrated in both nMOS (8.2Angstrom EOT) and pMOS (7.5Angstrom EOT) transistors. The metal-gated devices outperformed their polysilicon-based counterparts in terms of electrical performance parameters, including high conductance, low leakage and reduced threshold-voltage instabilities. Besides the elimination of gate depletion, the metal gates enhanced high-k scalability and significantly reduced gate-leakage by up to three orders of magnitude. Transistor drive current also improved significantly.

Dr Luc Van den hove, Silicon Process and Device Technology vice-president at IMEC, comments: "These results show that tremendous progress - especially in terms of transistor drive current performance and threshold-voltage stability - has brought the concept of high-k metal-gate devices for both high-performance applications and low standby power close to real implementation."

To realise sub-1nm EOT scaling, appropriate interfacial oxide control both before and during high-k deposition was applied. The lowest EOT values were typically obtained using a 'minimal interface approach' with minimal EOT contribution. In order to achieve this, scaled chemical oxide interfaces with controlled thickness and precisely controlled deposition and annealing conditions were used. HfO2 was deposited by atomic layer chemical vapour deposition (ALCVD).

nMOS performance indicators slightly exceeded those for poly/SiO2-based devices while significant improvement was seen in pMOS performance since hole mobility remained constant down to the lowest EOT values. In addition, not only the initial performance but also the threshold-voltage instabilities due to trapping were strongly reduced as compared to typical results on high-k films with polysilicon electrodes.

Part of this research was done in collaboration with IMEC's high-k industrial affiliation programme partners International Sematech, Renesas, Matsushita and Samsung.

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