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Molecular Engineering For Low- And Ultra Low-k

A wide variety of inorganic and organic films that have high temperature stability have been proposed for both spin-on and chemical vapour deposition (CVD) low-k and ultra-low-k (ULK) applications [1]. Thus far, the only materials capable of successful integration in copper dual damascene processing have been inorganic films with k values greater than 3.0. Sub-90nm generations of IC manufacture need effective k values substantially lower than this.

A common and relatively simplistic approach is to use porogenation processes that introduce void volume (pores) into the film. These porogen-based approaches have all failed in IC process integration for various reasons and new approaches are needed to avoid the pitfalls associated with porous films. One way to achieve low-k and ULK films that have the desired mechanical properties for process integration is molecular engineering.

Problems with porous films

In the ULK films developed to date as much as 40% porosity may be introduced to achieve k values around 2.2 - usually at the expense of significant sacrifices in the materials' mechanical properties.

Porogenation commonly employs techniques that burn out organic molecules at elevated temperatures to generate relatively large holes in the film. It is well known that for most low-k materials the dielectric constant has an almost linear relationship with porosity and that mechanical properties (e.g. modulus and hardness) are a power function of porosity. Thus while dense CVD oxide has a modulus of 70GPa and a k value of 4.0-4.2, most films with k values ~3.0 have less than 10% porosity and modulus values of 5-15GPa. Most mesoporous films with k values less than 2.5 have 30-50% porosity and modulus values of only 1-4GPa. The International Sematech (ISMT) guideline stipulates a modulus of 4GPa to pass blanket and patterned chemical mechanical planarisation (CMP) with acceptable yields.

CMP is a huge integration challenge for low-k dielectrics. High porosity volume results in stress voiding in the dielectric after metal CMP, particularly in smaller features, and is associated with damage to the porous dielectric during via etch. Stress voiding does not occur in dense siloxanes that have only intrinsic porosity.

In addition to mechanical shortcomings, there are other problems associated with highly porous films. These films are subject to high etch rates and are prone to carbon depletion during via and trench etch. Even though the etch process is anisotropic, carbon depletion occurs at the sidewalls damaging the integrity of the dielectric. This damage results in larger pores at the sidewall, higher leakage and higher k and moisture absorption into the film, preventing timed etch processing.

Fig.1: Carbon depletion during trench etch with mesoporous low-k and added buried etch stop process

Carbon depletion results in film damage at the bottom of the trench during trench etch. To avoid this damage, a thick buried etch stop layer must be added resulting in not only an increase in the number of process steps from one to three, but also in a large increase in the effective k of the dielectric stack. Furthermore, the buried etch stop process does not help prevent damage to the sidewalls of the porous films. Carbon depletion in low-k dielectrics increases as a function of porosity and is minimised in dense films.

Back to fundamentals - molecular engineering

With so many issues facing the integration of porous films, it is difficult to envision how these can ever be integrated into standard IC processing. Even if the porosity is not introduced until after completion of metallisation processing, it is still questionable whether the porous dielectric stack can withstand the rigours of packaging. Is there a better way to achieve the desired ULK values and thermal-mechanical properties without the introduction of porogenation?

An alternative approach to porogenation is to engineer the precursor molecules up-front to afford the properties that are desired and needed by the industry. Figure 2 provides a graphic depiction of how precursor molecules are designed and combined to achieve these results. This approach forms the basis of a new materials science technology and products being introduced under the SLX series. These materials are based on a silsesquioxane back-bone structure, containing modified novel moieties to provide specific desired properties for the final ULK material.

Fig.2: Graphical illustration of the molecular engineering approach used to develop SLX22

The design features of these materials include tuning polarisabilities, balancing orientational polarisabilities, minimising molecular asymmetries and tuning intramolecular controlled free volume. High cross-linking densities can improve thermo-mechanical properties and prevent pore formation caused by loss of functional groups. Highly stable bridging groups can reduce the coefficient of thermal expansion (CTE) to achieve a match with interconnect metallisation and also enhance mechanical properties and thermal stability.

Using molecular modelling allows for the engineering of film precursors that have low pore volumes equivalent to dense films at ultra low-k values and give the desired mechanical properties. A modulus of more than 6.0GPa has been demonstrated for an ULK dielectric material with thermal stability that exceeds 470¼C and average pore size of less than 1.5nm under a very narrow and controlled distribution (Figure 3). A CTE of 15ppm/¡C makes this material compatible with both copper and aluminium metallisation. A summary of key fundamental properties of these materials at dielectric constants of k=2.8 and k less than 2.4 is given in Table 1. Most importantly, these two materials have significantly different bulk dielectric constants but demonstrate very similar fundamental properties. This has significant implications with regard to integration robustness and extendibility of these materials for subsequent IC design generations.

Fig.3: SLX22 pore size distribution derived through elipsometric porosimetry for a k=2.3 film with <15% pore volume and modulus of 6.4GPa

Process integration with SLX materials

To prove the integration robustness of the SLX materials a broad range of tests have been run in the test facilities at VTT Microelectronics in Finland and at Cypress Semiconductor in San Jose, California. The results have been documented in a jointly authored White Paper [3]. Experiments were run using a combination of 100mm test wafers for film characterisation and module integration process development and 200mm patterned wafers supplied by Cypress Semiconductor for planarisation, gapfill and electrical testing. Table 2 summarises the measurements and tests that were done using material at a dielectric constant of 2.8.

Ashed and unashed spin-on dielectrics (SODs) received exposure to resist stripper and were subsequently capped with plasma enhance chemical vapour deposited (PECVD) SiNx. The stack did not show any signs of blistering after a 425¡C/5h bake in a diffusion tube. Consequently, any trapped solvent in the film outgassed quickly during the initial stages of the 300¡C PECVD SiNx deposition. The wafers passed the scribe and Scotch tape tests without incident. Results for thermal shock and prolonged bake tests were similar on bilayers of SOD with Al or SiNx. In every case, the SOD/Al, SOD/SiNx, Al/SOD and SiNx/SOD systems displayed no blistering and passed the tape test.

The CMP removal rate of the SOD blanket films using the metal polish recipe was 108nm per minute, with only 10% thickness difference from centre to edge (Figure 4) without process optimisation. On the same recipe, the rate compares favourably with that of other films. PECVD oxide, W, Ti, TiN, Cu and TaN all polish at a faster rate than the SOD. After polishing, the refractive index of the SOD shifted by approximately 0.02 from the unpolished samples, recovering after a short dehydration bake. The results suggest that the material has the potential to run uncapped, acting as a sufficient stop for metal polish.

Fig.4: Removal rates for SLX28 with metal CMP. Post polish thickness range less than 10%

Etch rates on both patterned and unpatterned substrates closely matched that of PECVD oxide films. Figure 5 shows an SEM micrograph of a via etched using a standard TEOS CF4 + CHF3 + Ar discharge on a parallel plate etcher. Good vertical sidewalls are obtained from the via etch.

Electrical testing of Cypress Semiconductor's five-terminal device used for measuring in-plane capacitance between metal lines gave a 30% drop in capacitance for SLX28 as the dielectric vs. the same structure using a voided TEOS dielectric. Further proofs of robustness yield via structures from the Cypress 250nm Al process. Figure 6 shows probability plots for SLX28 using two different ash recipes. Via resistance was comparable to CVD oxide for the same process. Initial tests with SLX22 on VTT test structures at 1µm give equivalent yield and via resistance to CVD oxide. Further studies are in progress for sub 250nm integration for both Al and Cu metallisations.

Table 1: Summary of key fundamental properties at dielectric constants of 2.8 and less than 2.4

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