EEPROM cell shrunk to 1.2mm2
The memory cell is up to four times smaller than conventional EEPROM, providing up to 2Mbits of EEPROM in silicon areas compatible with the cost constraints of smart card applications. Further, Philips has already succeeded in shrinking its non-volatile memory technology from 0.18microns to 0.15microns. Early indications lead the company to expect that it will also migrate to 0.13microns and even below 100nm.
"With embedded ROM, EEPROM and Flash memory available in the same low-cost CMOS process for all our 8-, 16- and 32-bit product families, we can implement a wide range of non-volatile memory configurations for advanced smart card applications, especially in the banking, e-government and mobile markets," says Bettina Kuhrt, marketing manager for Mobile Communications Products, Security Solutions.
Philips’ new EEPROM process uses a similar memory cell design to the company’s 2-transistor NOR-cell Flash memory technology that uses Fowler-Nordheim electron tunnelling for both programming and erasure to achieve low power consumption. The main differences are increased gate area on the memory transistor to increase charge injection, closer control of the erase distribution and read threshold voltages and a small increase in programming voltage. Philips is claiming a breakthrough in byte-erase time for Fowler-Nordheim tunnelling devices of less than 1ms. Conventional 0.18micron EEPROM technology achieves a typical cell size of 5mm2. Philips’ new embedded EEPROM cell is only 1.2mm2 – four times smaller.
"None of the techniques used in our new Flash/EEPROM memory option compromise the performance of our current CMOS18 baseline process, making this a true embedded memory technology that is highly reliable in the field," says Frans List, strategic program manager for Embedded Memory. "In smart card applications, where cards are often subjected to harsh electrical conditions and where the cost and inconvenience of card-replacement is high, reliability is an important factor."
Philips’ new CMOS18 EEPROM memory option is available for design-in now and is supported by all the company’s CMOS18 design tools, including the provision of memory test facilities through a standard JTAG interface.
Smartcards need increased capacity to deal with new security measures such as inclusion of biometric data, while working on low power, particularly in contactless applications where the only power available is the electrical energy from the local radio frequency (RF) field.
