Dry etch for the 65nm photomask future

Wafer scanner exposure systems are currently able to print 90nm technology node features with new 193nm wavelength argon-fluoride excimer laser light sources. Thus the features are smaller than wavelength of the light used to create them (subwavelength resolution). Recent trends indicate that this lithography technology is extendible to at least to 65nm node features. Some in the industry believe novel optical adjustments to wafer scanners - immersion lenses using water - will allow this technology to go even to 45nm feature sizes!

Through all this, the venerable photomask is expected to remain the primary transfer medium for mass-producing integrated circuit patterns. Of course, wafer lithography now requires the use of newer photomask techniques such as phase shifting in order to achieve the very small features demanded by the current International Technology Roadmap for Semiconductors (ITRS).

Now, more than ever before, etching binary chromium (Cr) masks is the resolution-limiting step within the manufacturing process of advanced masks sets. Again, suppliers across the industry has worked hard to surpass the current ITRS roadmap. Unaxis Semiconductors has brought the 65nm technology node within reach more than one year earlier than predicted. We expect 90nm node technology masks to be prototyped before the end of 2003 and 65nm masks to be prototyped by the third quarter of 2004 - 12 months earlier than the most recent roadmap!

Developing a solution

For more than 12 months, the Unaxis Semiconductors' photomask strategic business unit (SBU) has been developing new etch technology focused on the 90nm and 65nm nodes. The company believes that this fourth generation (Gen 4) inductively coupled plasma (ICP) system is quite unique and will allow customers to push the limits of optical lithography.

Three major manufacturing technologies are used in the production of photomasks. Pattern generation writes the circuit pattern information into a resist layer on the mask blank. The resist is developed in a wet chemical process. Finally, the photo absorber (of Cr, MoSi, etc.) is etched in a wet chemical or ICP dry process. The developed resist is used as an etch mask in the last step.

Each of these manufacturing processes contributes a portion of error to the formation of the actual vs. ideal pattern. Any pattern deviation is typically known as the mean-to-target error, where "target" describes the various feature sizes and placement of the circuit pattern as originally designed on the computer. The "mean" aspect describes how the manufacturing process(es) altered those features and their placement on the final mask. Obviously, as features sizes have continued to shrink, the allowable "mean-to-target" error budget has had to shrink proportionately. This has posed a significant problem in general for all mask manufacturing processes, but has posed a particularly difficult problem for the mask etch process.

In terms of pattern generation, the accuracy of exposure tools has improved significantly over the past five to ten years with smaller grid and beam sizes, enabling these tools to describe ever smaller features in the resist and place those features in more closely controlled proximity. However, resist systems have not evolved in concert with the beam placement accuracy of the pattern generators. In recent years, the important advances in resist chemistry have been in the form of "fast" resists which can be exposed with low beam energy (chemically amplified resists, for instance). However, almost no advancement has occurred in resist materials as it pertains to final image formation, resist thickness, feature sidewall angle, residue, material stability, etc. - all things that would make the etch step easier. The net result is that while pattern generator accuracy has improved substantially with regard to placement and overlay accuracy, these tools cannot fully absorb their fair share of the smaller error budget needed for overall feature fidelity (CD uniformity, feature resolution, feature size linearity, etc.) at the 90nm technology node. With no new resist systems in sight, they cannot be expected to absorb any further error margin as we move into 65nm technology node mask making.

The minimal evolution of resist systems equates literally to zero advancement in the method and accuracy of the resist-develop process. This step has not and will not be able to absorb any additional reduction in error budget.

Therefore it is painfully clear that the only manufacturing step left to absorb the ever smaller error budget needed to meet the 90nm and 65nm mask making challenge is the final etch process. One of the foremost advances in absorber etch technology came from Unaxis Semiconductors in 1995 with ICP dry etch technology. Since that time, Unaxis has introduced three successive generations of improved dry etch systems. Now, the collapsing ITRS roadmap has forced us once again to reduce the error tolerances in our equipment technology.

Figure 1 illustrates the evolution of dry etch error margins required for key performance parameters at the various technology nodes over the past eight years (Gen 1-3) and the error margin requirement today and in the near future (Gen 4). Dramatic performance improvements in dry etch system technology were required - and achieved during the past eight years.

Figure 1: Evolution of dry etch error budgets for key performance parameters at the various technology nodes over the past eight years

Feature size resolution and linearity

One subwavelength resolution method uses special mask materials that provide half-wave attenuation or "phase shifting" of the stepper light. Another, more common method, is to employ what are called "optical proximity correction" (OPC) features on the photomask. These are printed features on the mask which are too small to resolve at the wafer level but that add light to the edges and corners of very small features on the wafer. This "light assist" technique has been used effectively by pattern designers for many years.

What has become problematic for mask makers is that as average feature sizes decrease, OPC feature sizes on the mask are becoming too small to resolve. Figure 2 illustrates typical OPC features on an advanced photomask for a 0.13µm technology node device. Some of the OPC features shown are less than 200nm wide. As we move to the 65nm technology node, OPC features will shrink to less than 100nm. Very high resolution dry etch is the only answer.

Figure 2: Optical proximity correction (OPC) serifs add light at edges and corners of printed features

Another challenge facing the photomask industry as geometries diminish is the variety of small to large features on the same pattern level, which must be precisely sized. For technology nodes with features larger than 0.15µm, the average mask level would typically have only one primary feature which needed to be sized as closely as possible to the original circuit design parameter. All other features on that mask level, smaller or larger than the primary feature could be slightly under or over-sized because their dimensions were relatively inconsequential to the final device performance. This is no longer the case at 90nm. For example, on a 90nm mask, the primary design feature together with its various OPC features must all be sized as close as possible to their original design criteria because the margin for error on the wafer is so small. Figure 1 corroborates this new challenge. Note that in 1998, at the 0.15µm technology node, critical dimension (CD) linearity was not even a specified performance parameter. By 2001, CD linearity appears as a mask etcher performance requirement at less than half the total etch bias. This requirement continues to drop dramatically with each new technology node.

Bright field/dark field linearity

The Gen 3 MASK ETCHER III was an enormous breakthrough for the mask industry. This tool was able to optimise the plasma etch of chromium films on glass so that the uniformity for high and low load Cr patterns are the same. This was a major step forward and provided a large yield improvement for most mask shops. This was at a time when most device pattern layers were fairly uniform across each mask, creating evenly distributed high or low chrome loads on different masks. However, as device geometries have grown smaller, device designs have grown more sophisticated. Many logic devices now have large embedded memory cells and memory devices have on-board logic circuits. The net results of this circuit integration are patterns with large open cells on the same layer, creating masks with large areas of unevenly loaded chrome. In other words, mask makers are now faced with high and low chrome loads on the same mask.

Figure 3 is a picture of the "Ybor" Unaxis Semiconductors dry etch test mask used to emulate the high/low chrome load conditions of an advanced mask layer. The test features are written in FEP171 chemically amplified (e-beam) resist. There are 64 measurement sites covering a 135x135mm patterned area. Each site contains a variety of iso/dense and clear/dark features. This kind of pattern layer is aptly named a "nightmare" mask level by the industry. As device designs evolve, mask makers are seeing more and more of these advanced mask levels.

Figure 3: Highly uneven pattern with more than 99% chromium load in window and less than 1% Cr load on remaining area

It is desirable for this type of mask layer to achieve a very low total etch bias in both the clear field (window) and the dark field (low Cr load area), while at the same time producing a very low CD uniformity for the full range of feature sizes (linearity). The Cr profile must be kept as close to 90¡ as possible.

Why Gen 4?

Until now, the required dry etch process improvement has not been forthcoming to support the performance level needed for 90nm lithography. As good as Unaxis' Gen 3 ICP reactor is, asymmetrically loaded etch is a challenge.

Figure 4 is a box plot which gives a pictorial representation of the dry etch contribution across an Ybor (1 window) test mask (#1322) using a Gen 3 ICP source. The various box sizes illustrate the relative CD uniformity of 0.5µm features across the mask based on the amount of under or over etch of each feature from the average etch bias. The average etch bias appears quite good (26.22nm) but global CD uniformity is quite high (23.14nm, 3s). After more than two years of process development, the dramatic chrome load distribution on this type of mask level continues to pose a severe CD uniformity problem for Gen 3.

Figure 4: Best Gen 3 dry etch process shows very large bright-/dark-field etch signature in clear window vs. dark outer area

More than 18 months ago, Unaxis came to an understanding of some of the very fundamental concepts that need to be realised for a new etcher, Gen 4, aimed at 65nm mask making. Using a unique, advanced plasma ICP concept (Unaxis patent pending), even early Gen 4 results demonstrated resist selectivity two or even three times normal process conditions. Furthermore, Gen 4 incorporates a vastly improved vacuum system and uses a radically new RF generator arrangement allowing us to explore process areas that were not possible in Gen 3. The proof is in the process performance results.

Figure 5 is a box plot of the dry etch contribution across an Ybor (1 window) test mask (#1396) using a Gen 4 ICP source. Telltale etch disparity signatures in the window area are notable absent. The average etch bias is still quite good (31.78nm) but the global CD uniformity is now almost half (12.19nm, 3_) of that typical for Gen 3.

Figure 5: Initial Gen 4 dry etch process shows almost no bright-/dark-field etch signature disparity in clear window vs. dark outer area

Figure 6 is a more complete summary comparison of results for the two Ybor test masks #1322 and #1396. The summary includes measurement data for 300nm, 500nm and 1500nm features across each mask. In each case, the CD uniformity from the Gen 4 etch is vastly superior to the Gen 3 results. The total feature size linearity is ~3nm (range) across the various feature sizes for the Gen 4 etch results - a 4x improvement over Gen 3.

Figure 6: Dry etch feature size linearity - Gen 3 = 12nm, Gen 4 = 3nm