Info
Info
News Article

Porous CVD Ultra Low-k For 65nm And Beyond

Reducing k values of dielectrics below 2.5 presents major semiconductor process challenges. The need to introduce pores into low-k materials creates serious process weakness. Keith Buchanan of Trikon Technologies describes some of the factors involved and possible solutions for his company's Orion low-k dielectric.


Chemical vapour deposition (CVD) can be used to produce nano-porous, ultra low k (k<2.5) films to meet the requirements of sub-90nm technology interconnects. Process optimisation allows the tailoring of such film properties as carbon content and pore size distribution, and these in turn strongly influence the film's mechanical properties. The CVD ultra-low k films are well suited for use in advanced dual damascene interconnects using via-1st integration with timed etch for the trench.



Orion is a family of nano-porous, SiCOH-type low k dielectric films deposited using Trikon's Planar P300 cluster tool and chemical vapour deposition (CVD) process technology. Developed for use in 65nm and 45nm technology node interconnects, the k value is tuneable from 2.8 to as low as 1.9.



Generically, Orion is a nano-porous, hydrogenated silicon oxy-carbide. The overall dielectric constant of the as-deposited film is a function of the dielectric constant of the matrix material surrounding the pores, and of the volume porosity (kpores assumed to be 1.0). Incorporation of significant porosity is needed to produce films with k values less than 2.5.



However, the deposition process must also be tuned to maximise hardness and elastic modulus - these properties largely determine the resilience of the low k films to the mechanical stresses imposed by chemical mechanical planarisation (CMP) and packaging. Film hardness and elastic modulus are dependent on both the carbon content of the films and on the volume porosity and pore size distribution. Control of pore size distribution will also influence ease of integration through process steps such as wet cleans and metal barrier deposition. It is therefore necessary to carefully engineer the CVD process to optimise k along with the mechanical and electrical properties of the film.



Figure 1 shows Si-CH3 absorbance data comparing a 'high' carbon low k film with a 'low' carbon process. Although both processes produce films with dielectric constant 2.1-2.2, the films with less carbon are significantly harder. The interaction between k value, pore size range and hardness is demonstrated in Table 2, where hardness values are given for three Orion film variants. All three films were deposited using the same tool hardware and precursor gases and the hardness variation is achieved through process recipe tuning. Film hardness is seen to be a function of pore size range. Films with the smallest average pore size and smallest pore size distribution give the greater hardness values. By varying the CVD process conditions, film hardness can be varied by a factor of five with less than 10% variation in k value.










Fig.1:
Film hardness vs. FTIR spectrum integrated methyl peak intensity, normalised
to Si-O



Integration

Via-first dual damascene is a favoured integration scheme due to its being relatively tolerant of via-trench misalignment. For 65nm interconnect technologies and beyond, use of a trench etch stop layer is not practicable because of the negative impact on effective k value. Avoidance of the trench etch stop layer also eliminates two interfaces from the dual damascene stack and this is potentially beneficial for mechanical and electrical reliability.



When the same low k material is used at both trench and via level, and in the absence of a trench etch stop layer, the development of a production-worthy timed trench etch process is challenging. It must be sufficiently controllable to give repeatable profiles across 300mm wafers. Also, the trench is stopped in the nano-porous low k dielectric and the etch process must be optimised to maintain a smooth etch-front. The optimised trench etch process used in dual damascene integration with SiC etch stop layer will not necessarily be useable when the etch stop layer is removed (Figure 2a). However, with process re-optimisation, excellent profiles can be obtained (Figure 2b).










Fig.2:
Non-optimised (a) and optimised (b) timed trench etch profiles demonstrating
a smooth etch front in nano-porous Orion 2.2 low-k. Etch chemistry is
CF4/H2/Ar



Compatibility with CVD metal barriers

Use of porous low k dielectrics makes integration of the metal diffusion barrier more challenging. To maintain acceptably low line effective resistivity in local interconnects, the barrier thickness must be 10nm or less, according to the International Technology Roadmap for Semiconductors (ITRS). Deposition of such thin layers into features etched in relatively dense (non-porous) low k dielectrics does not present a significant integration challenge. However, when porous low k dielectrics are used, the trench and via sidewalls of the porous low k dielectric must be 'sealed' so that the barrier cannot be penetrated by copper. Barrier penetration into porous low k dielectrics can be exacerbated by too large a pore size and also by the use of highly conformal CVD barrier deposition processes, especially atomic layer CVD.



Sidewall sealing can be accomplished by the deposition of a thin, conformal layer of dense dielectric. The required thickness will depend on pore size and the addition of a denser film will increase the effective dielectric constant between the metal lines. The inherent properties of the Orion 2.2 low k dielectric allow a different approach to pore sealing to be used. Studies show that trench sidewall sealing in Orion 2.2 can be achieved in-situ during etch/resist strip processing.



A magnified 'detail' image highlights the localised densified region on the trench sidewall (Figure 3). The densified layer is 5-8nm thick with the thickness dependent on the resist strip chemistry and processing conditions. The etch chemistry is CxFyHz and densification is achievable with a resist strip chemistry. Through-focus TEM imaging shows the densified layer to be non-porous while elemental analysis of the TEM foil by electron energy loss spectroscopy confirms that the densified trench sidewall is carbon-depleted and oxygen rich compared to the neighbouring porous low k material. Electron energy loss spectroscopy (EELS) data confirms that a MOCVD TiN(Si) copper diffusion barrier deposited over the densified trench sidewall does not diffuse into the porous low k dielectric (Figure 4).










Fig.3:
Cross-sectional transmission electron microscope (XTEM) image of damascene
trench with Orion 2.2 porous low k and 8nm MOCVD TiN(Si) barrier










Fig.4:
a) XTEM showing 8nm MOCVD TiN(Si) diffusion barrier in a damascene trench
etched into Orion 2.2. b) EELS Ti spectrum measured along axis A in (a).










Table
1: Properties of an Orion 2.2 film targeted for 65nm technology










Table
2: Film hardness as a function of pore size distribution and k value


AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.

REGISTER FOR FREE

VIEW SESSIONS
Onto Innovation Announces New Inspection Platform
DISCO's Completion Of New Building At Nagano Works Chino Plant
Cadence Announces $5M Endowment To Advance Research
SUSS MicroTec Opens New Production Facility In Taiwan
New Plant To Manufacture Graphene Electronics
Siemens And ASE Enable Next-generation High Density Advanced Package Designs
ASML Reports €14.0 Billion Net Sales
South Korean Point Engineering Chooses ClassOne’s Solstice S8 For Advanced Semiconductor Plating
Obducat Receives Order For Fully Automated Resist Processing Tool From A Customer In Asia
Will Future Soldiers Be Made Of Semiconductor?
Panasonic Microelectronics Web Seminar
Belgian Initiative For AI Lung Scan Analysis In Fight Against COVID-19 Goes European
ITRI And DuPont Inaugurate Semiconductor Materials Lab
Can New Advances In CMOS Replace SCMOS Sensors In Biomedical Applications?
Tescan And 3D-Micromac Collaborate To Increase The Efficiency Of Failure Analysis Workflows
K-Space Offers A New Accessory For Their In Situ Metrology Tools
EV Group Establishes State-of-the-art Customer Training Facility
U.S. Department Of Defense Partners With GLOBALFOUNDRIES To Manufacture Secure Chips At Fab 8
Imec Demonstrates 20nm Pitch Line/Space Resist Imaging With High-NA EUV Interference Lithography
TEL Introduces Episode UL As The Next Generation Etch Platform
Changes In The Management Board Of 3D-Micromac AG
GOODFELLOW Confirms Membership In The BSI UK Graphene Group
Tower Semiconductor Announced Program Creating An Integrated-Laser-on-Silicon Photonics Foundry Process
AP&S Expands Management At Beginning Of 2021

Info
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
 
X
Info
X
Info
{taasPodcastNotification} Array
Live Event