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Companies Collaborate To Make 45nm

It is getting harder to stay at the forefront of the semiconductor game. Even the biggest companies now have to collaborate in some form. IMEC has just launched an initiative to put itself at the centre of this collaboration for 45nm and beyond. Mike Cooke reports from IMEC's Annual Research Review Meeting...

Economics has always been central to the semiconductor industry equation. By producing more out of less - more, faster products from smaller, less costly components - huge profits have been made. This has been possible because the technology has existed to transition to new, better products for relatively low cost. Now, this is becoming harder and highly competitive companies are being forced to collaborate.

The world-leading IMEC research centre in Belgium has become an expert in handling such collaboration. So it is no surprise that its new sub-45nm research platform has already attracted support from leading companies in Europe, the USA and Asia. In fact, the world's most profitable semiconductor producer - Intel - has joined as a 'Core Partner', along with Infineon, Philips, Samsung Electronics and STMicroelectronics. IMEC has a target of eight to ten core partners in all. Among these it is hoped that foundries and Japanese integrated device manufacturers (IDMs) will also choose to participate. The work will involve use of IMEC's 300mm "research foundry" facility currently under construction (Figure 1).

Keeping ahead

IMEC's programme targets technology generations two to three nodes ahead of state-of-the-art IC production (Figure 2). The central focus in these programmes is on advanced process module and device research, with several programmes being devoted to the exploration of new materials (Figures 3 and 4). Programmes include advanced lithography, cleaning and contamination control, substrate modules (implementation of high-mobility layers and advanced source/drain engineering solutions), gate stack (high-k dielectrics and metal gates), alternative CMOS devices (SOI and multi-gate FETs), germanium-based CMOS devices and advanced interconnect solutions (ultra-low-k materials and wafer-level packaging on copper damascene wires).

The tool set for the execution of these programmes will gradually transition from 200mm to 300mm wafers. The work will move to IMEC's new research facility as it becomes ready with equipment installation due in spring 2004 (Figures 5 and 6). Partnerships have been made with several leading equipment manufacturers who will deliver the latest process tools. Official inauguration of the new facility is currently scheduled for May 7, 2004.

The local Flemish government has invested EUR37mn in the facility. The cost of buildings and infrastructure is expected to be around EUR84mn. Equipment costs are put at hundreds of millions of Euros.


Core partner benefits include increased involvement in the steering and execution of the research, a favourable intellectual property ruling and an early insight to breakthrough results. The partners also have access to all the programmes allowing them to obtain a full picture of the status of sub-45nm technologies and to gain fundamental understanding in each area. Other semiconductor companies such as Texas Instruments are also participating in a large number of programmes.

Professor Gilbert Declerck, president and CEO of IMEC, comments: "These agreements are proof of our ability to bring together the leading semiconductor manufacturers, material and equipment suppliers. We are confident that more key players will join us and further extend our programmes with world-wide competencies."

Dr Paolo Gargini, Intel's director of Technology Strategy and Intel Fellow, says: "We believe that IMEC is indeed one of the world's centres of excellence in its field. Intel has been an active participant in IMEC programmes for many years and has benefited as a result. We believe that the new 300mm cleanroom - hosting programmes aimed at features of 45nm and below - will further enhance the value of the contributions from IMEC. We now feel confident that we will get maximum value by becoming a core partner together with some of the leading IC companies in the world."

Joel Monnier, corporate vice president and director of Central R&D at STMicroelectronics, reports: "In conjunction with ST's well-established and long-term co-operation with its strategic research partner LETI, the Crolles2 Alliance partners will now have access to the most efficient advanced R&D in Europe and the US."

Crolles2 in France involves ST, Philips and Motorola with the Taiwan foundry TSMC also participating. In fact, it is not the goal of the IMEC research platform work to create fully optimised 45nm processes - that is the job of the companies themselves and their collaborations such as Crolles2.


IMEC has struck a separate deal with Philips for a 45nm CMOS joint research programme. Work with Philips has been common at IMEC, going back to the establishment of the organisation. The CMOS45 Philips collaboration follows similar joint work at 65nm (CMOS65). However, new technologies are expected to play a bigger role, such as strained silicon on silicon germanium. For the gate, a high-k material may be used (or not) instead of the SiON created by decoupled plasma nitridation (DPN) used at 65nm.

Metal gates rather than polysilicon are likely to be used. A two-metal solution will be used to match to n and p transistor structures. For ultra-shallow junction implant annealing, two options are to be investigated - solid phase epitaxial regrowth (SPER) and "dynamic surface anneal" (DSA) that uses a combined lamp and laser approach. Results and explorations from the wider 45nm programme will clearly feed in to this more detailed work. Tool companies involved in the Philips programme include Applied Materials (oxynitride formation) and LAM Research (TaN etch on SiON).


Under a strategic alliance, ASML will provide advanced lithography clusters to the various 45nm programmes. This will involve research in both extending 193nm lithography through the "immersion" technique and the development of 157nm technology. At 193nm, water seems to be the ideal liquid for immersion. For 157nm, water definitely won't work.

Immersion has only been on the lithography agenda for about a year. The problem is that while on paper the technique offers higher resolution, all sorts of problems could emerge in bringing it to production. After all, dry 193nm lithography itself is really only just coming to mainstream production with the ramp-up of 90nm processes - years after what was expected when the technology was being developed. Some possible problems include the manufacture of huge lenses to accommodate the large numerical apertures and liquid handling (defects, vibrations and bubbles). The lithography industry is currently carrying out feasibility studies with a clear position expected from the major scanner producers by the end of the year.

Some IC producers (Intel, TSMC, . . .) have apparently used the promise of immersion to argue that they won't need 157nm in any form. The plan in this case is presumably to push 193nm with immersion and then move to extreme ultraviolet (EUV) technologies. IMEC plans to start work on an alpha EUV tool in 2006, aiming at 32nm processing.

Beyond the traditions

While the focus of the IMEC's current programmes is on extending existing technology, the researcher centre's leadership and staff are well aware that there are some big changes on the horizon. Some involve new design methodologies, others new approaches to technology development.

On the design side, IMEC has developed techniques to climb over the interconnect brick wall produced by the difficult integration of copper wiring with low-k intermetal dielectric. By placing components of an integrated circuit design closer to where it is needed, timing delays and power losses become less of a problem. The research centre has seen three-fold power savings from dividing buses into segments that can be turned off and by placing high-activity memory sections closer to the data path.

Declerck points out that while the physical processes of the semiconductor industry have been driving down feature sizes, chemists and others have been building upwards from the fundamental elements (Figure 7). When the two lines of development meet around 2010, a whole host of new possibilities become possible - what Declerck describes as the 'big bang of microelectronics' - covering magneto-, polymer -, opto- and nano-electronics, biosensors, molecular nanotechnology.

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