Infineon ISSCC contributions
The fully electronic DNA sensor has 128 positions with fully integrated, on-chip analogue-digital conversion for each sensor pixel. The demonstrated 16x8 CMOS sensor array can measure very low currents produced by the presence of target molecules. The company believes it provides a robust platform for a wide range of potential applications in biotechnology and pharmacological research. The fully electronic system is designed to be easier to use and less costly than current commercially available optical-based systems. The sensor pixel consists of a circuit that controls the sensor electrode voltages and provides amplified copies of the sensor currents at the pixel output.
For the RFID development, Infineon is aiming at a 1cent price tag, opening the way to barcode replacement. The Infineon RFID chip design uses circuits that are directly AC-powered. This eliminates the need for area-consuming circuit blocks for AC/DC conversion, including rectifiers, buffer capacitances, clock generator and power-up circuits. For a 96-bit memory design, meeting industry specifications for an Electronic Product Code (EPC), the AC-only approach enables a system design consuming a silicon area of less than 0.1mm2 when manufactured using a 0.13micron CMOS process. Infineon also describes a new packaging technology that uses a sidewall contact to facilitate the assembling process.
The ADC is claimed as the first working analogue circuit based on 90nm CMOS technology. A parallel layout of simple ADC structures achieves not only higher speeds but also new levels of power efficiency. Eight successive approximation-ADCs are put in parallel to get a high throughput at extremely low power. The Infineon researchers achieved a sampling rate of 600MHz at a power consumption of only 10mW. The figure-of-merit (FoM) of the ADC design – calculated to reflect power dissipation, effective number of bits and input frequency – shows the best value of all recently presented ISSCC publications, it is reported.
The four papers on high-speed communication circuits cover a four-channel ADSL2+ analogue front-end for the central office (CO), a power-optimised switched-capacitor 14bit delta-sigma modulator for ADSL CO, a fully integrated 13GHz delta-sigma fractional-N PLL and an 80Mhz, 10bit pipeline ADC. These four chips were built on a 0.13micron process.
