Infineon joins X
The X Architecture uses diagonal pathways, as well as the traditional right-angle ("Manhattan") configuration. The new technique is claimed to reduce the total interconnect wiring on a chip by more than 20% and via-counts (the number of connectors between wiring layers) by more than 30%, resulting in simultaneous improvements in chip performance, power consumption and cost. Preserving the Manhattan geometry for metal layers 1-3 maintains compatibility with existing cell libraries, memory cells, compilers and intellectual property (IP) cores.
Infineon fabricated its X Architecture test chip at Corbeil-Essonnes, France. Cadence Design Systems provided the test structure design, DuPont Photomasks and Infineon’s maskhouse produced the masks and Nikon's equipment was used for photolithography.
The pre-production phase of the design-to-silicon roadmap for the X Architecture - laid out by the X Initiative in 2002 - was completed in October 2003 with the announcement of functional silicon results by Toshiba. More recently, UMC became the first pure-play foundry to join the X Initiative and declared its readiness to accept X Architecture designs for fabrication at the 180nm, 150nm and 130nm process nodes.
The focus of the X Initiative's collaborative supply-chain preparation is now to enable broad adoption of the X Architecture for production manufacturing at both leading-edge (130nm, 90nm) and future (65nm, 45nm and below) manufacturing nodes. First production chips are expected in 2004.
