News Article

Low-downforce CMP For Copper/low-k Structures

Traditional high downforce (>2.0psi, 14kPa) chemical mechanical planarisation (CMP) processes face challenges when used to polish copper with low-k films in damascene interconnect structures. Peeling/delamination occurs in low-k films with weak mechanical strength due to the relatively high shear force. Additional problems include stress fractures and particle damage. Researchers from Applied Materials' CMP group describe a low-shear, low-downforce (<1.0psi, 7kPa) Cu CMP process that aims to solve these challenges, while remaining compatible with industry's productivity requirements - high removal rate and throughput...
One of the issues delaying the adoption of low-k dielectrics in copper damascene designs is that low-k materials are prone to damage during CMP. This damage susceptibility increases as the k-value goes down. Low-k materials have a much lower fracture threshold compared to SiO2 or fluorinated silica glass (FSG). As figure 1 shows, the decrease in k value brings about a dramatic reduction in bulk mechanical strength of the dielectric. Such greatly reduced toughness and hardness leads to the definition of the threshold shear stress that the material can withstand before fracture. Our experiments have shown this threshold to be typically about 10lb (45N) of shear force applied to a 300mm wafer. Further investigation of the relationship between shear force and downforce pressure for a variety of conventional CMP consumables (slurries and pads) showed the corresponding downforce pressure that produces the threshold shear force for 65nm-generation CMP to be approximately 1.2psi.

Decreasing k-value results in reduced

film hardness and toughness

Downforce pressures in copper CMP have decreased from 3-5psi for 130nm (SiO2 dielectric) to 2.0-2.5psi at the 90nm node with FSG or first generation low-k dielectrics. Further reduction in downforce to below 1.0psi is necessary for 65nm devices. Using a lower pressure reduces the shear force acting on the low-k film, diminishing delamination and stress fractures, as well as reducing particle damage to the soft dielectric surface (Figure 2). Particles (accidentals and slurry particles themselves) that barely scratch the wafer surface at 130 and even 90 nm nodes, creating nuisance defects, can cause total destruction of the entire wiring structure at 65nm because the dielectric is so much softer. To avoid such damage at 65nm, a much lower pressure is needed for polishing. In traditional CMP processes however, removal rate is directly proportional to pressure - simply lowering pressure causes throughput and productivity loss. This can be countered by increasing rotational speed.

Low-downforce polishing methods reduce delamination and stress fractures

High velocity for throughput and productivity

Advanced copper structures are typically polished using a multi-step sequence on separate polishing platens or stations and this technique was extended to low-downforce polishing - with variable pressures used in each step and within step sequences.

Linear velocity obtainable with three basic CMP tool concepts

Preliminary studies indicated that the reduction in removal rate (RR) from using a low-downforce process can be countered through increasing platen and head speed. An important consideration in assessing RR is the linear velocity between the pad and the wafer surface, not just the rotational speed - it is the linear velocity that goes into the governing equation for CMP removal rate (Preston's equation). Figure 4 shows the three basic CMP tool concepts from the standpoint of how they create this velocity. The rotation-based platform allows for much higher linear velocity. The velocities listed in the table are achieved at maximum rotational speed for a rotational platform (350rpm) and an orbital platform (600rpm). Although the orbital platform offers much higher designed rpm capability, its much smaller rotational radius allows it only 1/5 of the linear velocity attainable by a rotational platform.

Planarisation capability of low shear process

We found that to achieve acceptable productivity (at least 5000/min RR) at reduced downforce pressures (<1psi) and depending on the choice of consumables, the polisher needs to operate at rotational speeds of 200-350rpm. Conventional CMP platforms do not operate at such high speed and provide a polish process at 0.5psi and 60rpm which removes less than 1000/min. By increasing rotation speed from 100rpm to 350rpm, removal rate is increased from 1800/min to 5300/min, raising production to the levels that could previously only be achieved at substantially higher pressures (>2.0psi).

Rotational speed was also found to affect selectivity, especially where multiple interfaces are involved. For example, barrier removal may require balancing removal selectivity of three or four materials. An advanced damascene interconnect dielectric can require polishing of metals (Cu, TaN) and dielectrics (DARC and low-k films), all in one step, with a single slurry having different removal rates for various materials. While rotational speed can be an extra knob tuning the removal ratio for different materials, the 50 - 100rpm speed range of a traditional CMP tool is not wide enough to produce a noticeable selectivity change. The 350rpm speed of the low-shear process is high enough to see the removal ratio difference.

Process capability at low downforce

To determine the response sensitivity of the low downforce process, we tested for the effect on Cu removal rates. At a very low downforce range (0.3-0.5psi), a pressure change of 0.2psi resulted in a rate change of 650/min. This indicates that the process is quite sensitive to removal rate in the low downforce range.

Differential pressures applied controllably to different annular zones on the wafer have been shown in the past to effectively modify CMP removal rate profiles across the wafer to achieve desired post-CMP thickness distribution. This capability was thoroughly evaluated for the low-downforce regime. A range of profile changes were initiated by changing zone pressures in the range 0.8-1.3psi. We found an almost 50% change in removal rate can be introduced by just a 0.5psi change in zone pressure. It is possible to modify and maintain a desired polishing profile with selective application of zone pressures in the low-downforce operating regime.

The relation of step height reduction and Cu removal with two process regimes is shown in Figure 4. The solid line curve represents a traditional, 130nm-generation Cu CMP process (with alumina-based / hydrogen peroxide slurry) at 5.0psi and 93rpm. The dotted line data was from a low-downforce Cu CMP process using the same slurry at 0.8psi and 150rpm. It is evident that both curves followed the same trend, which suggests the low downforce process offers the same planarisation capability as a traditional high-downforce process.

Dishing and erosion result from overpolishing of local areas. While slurry chemistry and process parameters have significant impact on the final result, polishing pressure also plays an important role. Using the same polishing slurry and pad but different downforce, experimental results showed that reducing pressure from 1psi to 0.5psi caused average dishing to decrease by 200 and erosion to decrease by 100. Similarly, lowering downforce pressure from 0.8psi to 0.5psi reduced both dishing and erosion by 100. Lower dishing and erosion numbers translate to reduced metal loss in the wiring structures, which explains why sheet resistance from the low downforce process was lower than that from a higher downforce process (2.5psi) (Figure 5). Lower metal losses and larger remaining thickness of the lines allows for higher currents to be accommodated by the wires and more freedom for IC designers.

Sheet resistance of wafers polished with 0.8psi and 2.5psi processes

The benefit of using a low downforce process is not limited only to improved compatibility with fragile low-k materials that are used as dielectrics. As minimal metal structure sizes shrink with the progression of device nodes, adhesion of small copper lines to dielectrics and overall integrity of small copper lines becomes an issue. Direct experimental evidence shows that reduction of polishing pressure from 1.5psi to 0.5psi (Figure 6) allowed for complete elimination of copper pullout defects that compromise integrity of small copper lines and most certainly would impact yields.

Pattern Cu wafer defects vs. downforce (0.5psi vs. 1.5psi). At 1.5psi,
severe Cu pullout is observed (~22% of total defects) - at 0.5psi, there
is no Cu pullout seen


Lizhong Sun, Yufei Chen, Lei Zhu, Robert Jackson, Wei-Yung Hsu, and Konstantin Smekalin, CMP Group, Applied Materials.

AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.


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