Strained Silicon And Germanium On Insulator Partners
"Implementation of high-mobility layers and advanced source/drain engineering solutions in scaled planar devices" will investigate improved carrier mobility in strained silicon structures. The research covers strained Si formation on top of SRB (strain relaxed buffer) layers, silicide formation, shallow junctions and extensions, compatibility issues, advanced strain characterisation and device demonstration.
IMEC has already researched strained Si on SiGe transistors, ultra-shallow junctions and silicides and has developed a production technique for thin SRBs with a total thickness of less than 200nm. The structure achieved superior properties compared to the industry standard. SRB techniques can also be applied in a selective way on pre-formed isolation structures such as in shallow-trench isolation (STI). IMEC has also shown world-record mobility figures for holes in hetero-pMOS with strained SiGe.
The Ge CMOS devices programme targets the feasibility demonstration of fabricating Ge devices compatible with a state-of-the-art Si production line. These Ge devices will include high-k materials and metal gates to obtain aggressively scaled EOT (equivalent oxide thickness) targets.
The programmes will initially use 200mm equipment but will gradually transfer to 300mm tools in IMEC's new facility now under construction. Potential partners are leading IC and wafer manufacturers.
To support the germanium programme, IMEC, Soitec and Umicore have joined forces to enable fabrication of germanium-on-insulator (GeOI) substrates and development of semiconductor devices on these substrates.
Germanium has some attractive chemical and electrical properties as a potential replacement for planar silicon, which is unlikely to accommodate the rigorous scaling requirements of sub-45nm geometries. The material's carrier mobility is higher than that of silicon for both electrons and holes by two and four times, respectively.
This fundamental speed advantage of germanium over silicon has been known for decades - indeed, germanium bipolar transistors were common in the early days of semiconductor technology. However, the unstable nature of germanium oxide made the creation of metal-oxide-semiconductor MOS device structures unfeasible. MOS is the basis for low cost semiconductor production.
Germanium is expected to be compatible with high-k materials used as a gate insulator. Moreover, dopant activation temperatures are much lower than those required by silicon, facilitating the formation of shallow junctions. These features create a need for high-quality Ge-based substrates.
Soitec and Umicore will each contribute state-of-the-art technological expertise in their respective fields, sharing data and findings throughout the process. Umicore has a background in the commercialisation and development of germanium substrates and will be responsible for the development and production of 200mm and 300mm crystalline germanium wafers. Soitec will apply its proprietary Smart Cut process to transfer a germanium layer from these wafers to form a germanium-on-insulator (GeOI) wafer.
IMEC will bring its extensive knowledge of high-k materials, metal gates, device development and characterisation and process integration to develop a high-k layer deposition technique for GeOI substrates, as well as defect inspection techniques for the completed wafers. IMEC will also fabricate advanced devices to demonstrate the potential of GeOI substrates for the sub-45nm node.
"To solve the channel mobility and gate leakage current problems present in scaled silicon devices, we believe that alternative concepts such as the combination of high-k dielectrics with germanium need to be examined," says Gilbert Declerck, president and CEO of IMEC.
In March this year, a Soitec competitor in the SOI market, Silicon Genesis (SiGen) in the USA, detailed its own proposals to develop GeOI. SiGen has already produced and is shipping germanium-on-insulator (GeOI) wafers. These substrates are produced using SiGen's proprietary Plasma-Activated Bonding and Controlled Cleave Process to transfer a thin germanium layer onto an oxidised silicon wafer.
SiGen claims that next-generation high-k dielectric deposition technologies coupled with its new GeOI substrates offer device manufacturers the enhanced mobility of germanium without MOS gate oxide issues. Since the germanium layer is built on a silicon wafer, device manufacturing is immediately made practical by using silicon-based standard fab tools and processes.
Looking beyond SOI
Soitec is also working with ASM International on strained silicon technology in a programme started in May 2003. The companies already claim a major milestone in their partnership with samples of a first-generation strained silicon wafer for the 65nm technology node. The companies will now focus on fine-tuning strained SOI processes to optimise substrate performance, boost productivity and maximise cost efficiency. The aim is to accelerate time-to-market for a complete industrialised solution for 200mm and, ultimately, 300mm strained SOI wafers. Soitec's Smart Cut and ASM's Epsilon 3000 epitaxial reactor are used to produce the wafers.
The first product in Soitec's new portfolio of strained SOI substrates consists of a silicon germanium on insulator (SGOI) template substrate on which a final strained silicon layer is grown. The result is 200mm fully relaxed silicon germanium on insulator substrates incorporating 20% germanium with and without the final strained silicon layer. Preliminary R&D findings indicate excellent control over the homogeneity of the layer stacks, as well as strain reproducibility in silicon layers as thin as 15 nm.
Tailored for both partially depleted and fully depleted applications, these wafers will enable improved device performance, while shrinking critical dimensions and increasing chip density. Soitec's subsequent generations of strained silicon solutions will include SGOI with higher germanium content, strained silicon without the silicon germanium template layer, as well as germanium on insulator - all to be developed for the 45nm technology node and beyond.
In an effort to speed up industrial sampling, Soitec and ASM are operating in a "virtual fab" mode, processing 200mm and 300mm SGOI wafers at both company sites. Teams from both companies have joined forces to fine-tune the epitaxial processes and optimise the production process for high-volume fabrication. This "virtual fab" allows Soitec to secure early industrial sampling, bridging the time required to implement the infrastructure at Soitec's production facility. Once the epitaxial equipment is installed and the technology is perfected, high-volume production will commence at Soitec's facility in Bernin, France.