Matsushita joins IMEC research
Previously, Matsushita made a successful collaboration with IMEC on the development and implementation of high-k gate stacks for the (sub)-65nm node, which started in 2002.
Six integrated device manufacturers (IDMs) have agreed to be core members in IMEC’s sub-45nm silicon research programmes. Negotiations are ongoing with several others. Work will be carried out on high-mobility layer substrates, advanced source/drain engineering, high-k dielectrics, metal gates, silicon-on-insulator, multi-gate FETs, germanium CMOS devices, ultra-low-k and wafer-level packaging.
IMEC began construction of a 300mm cleanroom last year that will be ready for equipment installation this spring.
Professor Gilbert Declerck, president and CEO of IMEC, comments: "This extension of our research platform in Japan is an important step towards the further globalisation of IMEC’s sub-45nm research platform. By bringing together European, Korean, US and now Japanese semiconductor manufacturers as well, a world-wide consortium with adequate critical mass has been formed to collaborate on the most advanced research to stay in tune with the semiconductor technology roadmap, which is essential for this global semiconductor industry."