Bringing III-V expertise to silicon scaling
Aixtron has entered into a three-year joint development programme (JDP) with IMEC for using AVD for deposition of novel materials for high-k and metal gate stacks. Both dual and single metal gate options will be pursued.
Major milestones of this high-k/metal gate joint development programme will include:
* implementation of multi-component high-k dielectrics with polysilicon/fully silicided gate electrodes in planar devices aiming at equivalent oxide thickness (EOT) values in the range 1-1.5nm
* development of alternative multi-component metal oxides with higher k values in the range 25-50 for future scaling needs for EOTs down to 0.5nm
* development of optimised metal layers for implementation as dual or single metal gates in aggressively scaled devices
* exploration of the limits of scaling planar CMOS devices with metal electrodes targeting a 20nm gate length and EOT values down to 0.5nm
* deposition of advanced high-k/metal gate stacks on germanium substrates
The Aixtron Tricent platform features an AVD module for deposition of gate dielectrics such as HfSixOy and a module for metal deposition of advanced electrode materials such as Ru, TiN, and Ta(Si)N. Also included in the cluster tool will be a rapid thermal annealing module, including plasma nitridation and oxidation features, which will ensure flexible pre- and post-deposition interface engineering capability.
Professor Gilbert Declerck, president and CEO of IMEC, comments on Aixtron’s III-V experience: "We see this collaboration as a first step towards a more elaborated collaboration in the area of germanium-based devices for which profound deposition expertise of III-V materials is absolutely crucial."
"This programme represents an important complementary effort to Aixtron’s on-going high-k development activities within the MEDEA T207 programme at STMicroelectronics in Crolles, France," adds Tim McEntee, executive vice president and chief operating officer for Semiconductor Equipment at Aixtron.
