UMC boosts 45nm PMOS
A 70% hole mobility gain was demonstrated, resulting in a 30% increase in PMOS drive current. In addition to the performance gain, the company reports an improved distribution of device parameters, indicating an increased potential for future manufacturability. Moreover, improved noise characteristics make this method suited for analogue applications.
Details will be reported at the Symposia on VLSI Technology and Circuits to be held June 15-17, 2004, Hawaii.
The description sounds similar to a technique reported by IBM last year (Bulletin 498, September 12, 2003). In silicon, resistance to carrier flow is direction dependent. The easy current flow directions are different for electrons and holes. By bonding wafers with different crystal orientations and then carrying out etch and deposition steps one can create a substrate with different crystal orientations in different areas. One can therefore build the PMOS and NMOS transistors that make up CMOS with optimal substrate performance for each type.
In the past UMC has worked on technology with IBM and Infineon Technologies. More recently, however, it has tended to carry out (at least publicly) it own development work. IBMÕs relationship has continued with Infineon and has brought in SingaporeÕs Chartered Semiconductor in as foundry partner.