News Article
High-k progress in France
STMicroelectronics, CEA-Leti and Aixtron have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes.
STMicroelectronics, CEA-Leti and Aixtron have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes.
So far, equivalent oxide thickness (EOT) values of 1.15nm or 11.5Angstroms have been achieved based on hafnium dioxide / silicon dioxide / silicon (HfO2/SiO2/Si) stacks offering leakage current densities as low as J(L)=6.8x10(-2)A/cm(2) at 1.5V.
The new process significantly reduces transistor leakage current by the deposition of high-k gate-insulation material. The Advanced Modules team of researchers from ST and CEA-Leti at STÕs Crolles facility is using AixtronÕs Tricent reactor and Atomic Vapour Deposition (AVD) technology.
The HfO2 deposited layer process was developed in conjunction with Aixtron and the wafer processing and the characterisation were performed at CEA-LETI facilities in Grenoble.
