Process modelling to beat interconnect variations
The work is to meet the needs for developing next-generation processes for electro-chemical deposition (ECD) and chemical mechanical planarisation (CMP) that will require a much more detailed understanding of the causes of interconnect variation and solutions to mitigate those causes.
"IMEC has initiated this programme with Praesagus to help our core technology partners address a serious concern as they move to the next process node," reports Karen Maex, PhD, IMEC Fellow in the Silicon Process Technology division.
"The current design for manufacturing (DFM) communication paradigm of CMP design rules and worst-case thickness tech files is running out of steam and the recently proposed alternative of density-based models does not provide enough accuracy," adds Hugo De Man, IMEC Senior Research Fellow. "In our System-Level Integration programme, IMEC is researching the impact of process variability in deep submicron technologies on circuit and system level. Variability in interconnect RC delays is a main concern as we are scaling down technology beyond the 90nm node. Praesagus' expertise in physics-based modelling of interconnect technology offers a promising alternative to accurately predict the interconnect performance, serving as a critical input to system designers."
The term of the agreement is two years. IMEC Industrial Affiliation Partners will have early access to the technology and Praesagus expects to incorporate the results into their commercial product.
