Structured ASICs taping out to Europe
The complete product family is scheduled for released to production in early Q1 2005. The company has previously produced validation chips at STMicroelectronics. This product is being co-developed with Flextronics Semiconductor who will also be offering structured ASIC products and services.
eASIC developed its Structured eASIC to consist of an array of logic cells (eCells) with SRAM based look up tables (LUTs) and flip-flops. The eCells are inter-connected by a segmented wiring grid using upper metal layers that are customised per customer design with a single via-mask. Logic programming of the eCell is done similarly to an FPGA, by loading a bit-stream to program the LUTs and flip-flops after powering up the device.
A customer design is implemented on the Structured eASIC fabric by using a combination of a bit-stream to program the LUTs and a single custom via-mask to customise the routing. Via-customisation can also be performed by direct-write e-beam lithography, avoiding soaring mask costs for small runs.
The FA1 has 600k usable ASIC gates, 372 I/Os and four phase-locked loops (PLLs). Target gate speeds are for a fast input to output of 60ps and an average gate delay of 80ps. Operating frequencies are put at 400MHz with power consumption rates at 20nW/MHz/gate. Typical system power is quoted as 350mW.
