High speed conversion
High data transfer rates are needed in various serial communication applications such as the read channels of hard disks that rely on digital signal processing circuitry. These circuits require high speed ADCs to provide the interface between the analogue and digital parts of the system. It is desirable to realise these integrated circuits in standard CMOS technologies to allow low cost production and monolithically integration of ADC and digital signal processor (DSP).
In a classical n-bit Flash ADC only 2n-1 comparators with low input offset voltages are used to generate a perfect bubble-free thermometer code at the output of the comparator bench. To guarantee the demanded low input offset voltage, large active device areas must be used to reduce the effect of device mismatch within the comparators.
In contrast to this traditional approach, the new Infineon ADC with 6bit linearity uses 255 comparators with small active area. As a consequence, the input offset voltages are in fact higher, and a bubble-free thermometer code at the output of the comparator bench is not obtained, but the small sized comparators can be optimised for maximum operation speed.
In high-speed ADCs (>1GS/s), clock generation and distribution is a crucial point to meet the desired resolution. Since an uncertainty of the clock signal (jitter) directly translates into a reduction of the resolution of the system, the jitter has to be kept as small as possible. At an input frequency of 1GHz, a 6bit ADC needs to be clocked with a jitter of less than 1ps. Therefore, the new ADC comprises an on-chip LC oscillator with low jitter, which provides a complementary sinusoidal signal at a frequency of 4GHz.
Since only standard digital transistors are used, the ADC can easily be monolithically integrated in a signal processor without the need for analogue process options. Furthermore, the RF clock signal is generated on-chip and only a single supply voltage of 1.5V is used.
Infineon also presented papers on magnetic and ferroelectric memories and analogue CMOS along with a review of Multi Gate Transistors and Memory Cells for Future CMOS (invited paper).
