The growing volume of products requiring copper interconnects necessitates a high productivity electrofill.  Novellus researchers describe new chemistries

The transition to smaller copper interconnect features and low-k dielectrics presents increasing demands on copper electrofill process capabilities for void-free fill and formation of planar deposit topography. At the same time, the growing volume of products requiring copper interconnects necessitates a high productivity electrofill tool and process. J Reid, E Webb, J Sukamto, Y Takada, and T Archer of Novellus Systems describe new process chemistries designed to produce an initial rapid feature fill followed by gradually increasing levelling characteristics during a single step, single bath deposition process

During damascene interconnect formation, copper is electrodeposited as a continuous film across the seeded dielectric surface of wafers imaged with recessed patterns that define the chip interconnect circuitry. In the next process step, chemical mechanical planarisation (CMP) is used to remove all metal from the wafer surface leaving the desired Cu circuitry in the recessed dielectric images [1]. To most easily achieve rapid removal of copper and uniform definition of the Cu circuitry, the plated deposit should have a planar surface rather than a topography that depends on the underlying image in the dielectric. In practice, however, the plated copper film is typically recessed over large pads by an amount equivalent to the dielectric thickness, and is relatively thick relative to the field over dense arrays of trenches (Figure 1).

Fig.1: Cross sectional view of plated copper topography across a damascene wafer surface. The plated thickness is given by (A), the dielectric etch depth and corresponding reduction in plated thickness over large features is given by (B), and the overplating thickness over dense features relative to the field is given by (C)

Recessed areas in the deposit over large pads result simply because copper electroplating yields conformal deposits when aspect ratios are less than about 1:3 and the bottom-up growth characteristic of narrower features does not occur [2]. Little optimisation of this behaviour is possible without introducing mechanical polishing during electroplating. As a result, the thickness of copper plated in the field is usually at least equal to the dielectric depth. On the other hand, the increased plated thickness over densely spaced small features results when accelerator additives used to generate bottom-up fill remain locally concentrated on the surface after filling and continue to result in rapid deposition. This rapid growth, and the resulting overplating, can be reduced in numerous ways through modifications to the electroplating process.

Overplating reduction approaches include use of large slowly diffusing levelling additives and mass transfer conditions that limit leveller diffusion into features; application of reverse currents to displace accelerating additives from the copper surface following the completion of superfilling; pretreatment with accelerator additives followed by plating in levelling baths; plating sequentially in superfilling and highly levelling baths; and levelling additives that accumulate on the copper surface and gradually increase levelling activity after superfilling of small features is complete [3, 4, 5]. The goal of each of these processes is to maintain the initial very rapid bottom-up plating essential to void-free filling, but to halt the accelerated deposition process over dense features once the filling process is completed. Here, we discuss the advantages and limitations of these approaches, keeping in mind that the resulting process must be reliable and cost-effective for incorporation into a high-volume manufacturing environment.

Overplating reduction techniques

Slowly diffusing levellers:
Typical levellers used in Cu filling processes are much smaller than feature dimensions and can readily diffuse into the features. If too much leveller diffuses into a feature, the bottom-up fill associated with accelerator accumulation is halted due to current suppression by adsorbing leveller molecules. As a result, it is necessary to use relatively low concentrations of standard levellers such that a compromise between fill rate and levelling is achieved. As feature dimensions reach below 100nm, it becomes possible to choose slowly diffusing leveller molecules that have dimensions similar to the dimensions of the features themselves. Such molecules could strongly inhibit copper growth on the wafer surface while allowing accelerator accumulation and the associated bottom-up fill process to take place within features. Thus, only as a feature is filled and becomes planar with the field, will the leveller become effective. While this approach is realistic for very small features, a mix of feature sizes is normally present at a given metal level. If some feature sizes are significantly larger than the leveller dimensions, the leveller will diffuse into them and the effectiveness of the approach will diminish. While this approach to filling and overplating reduction may become viable for very advanced geometries, it is not a workable solution for 90nm and 65nm generation features.

Reverse currents:
It has been know for several years that the application of a brief reverse current results in the displacement or deactivation of accelerator species on the wafer surface. If a reverse current is applied immediately following the completion of filling, the excess accelerator on the copper surface over the filled feature is deactivated or desorbed and no further rapid growth over the feature takes place. As shown in Figure 2, smaller features undergo a complete bottom-up fill before larger features even begin filling. As a result, it is necessary to apply a series of reverse currents, each of which are timed to halt overplating over a different feature size. While this approach can eliminate overplating, the initial reverse pulses designed to eliminate overplating over small features actually displace the accelerator necessary for efficient bottom-up fill of larger features. This can result in seam voids in features that would normally fill without difficulty. In addition, reverse currents sufficient to displace accelerators can result in subsequent Cu growth irregularity and a variety of associated defects due to non-uniform re-adsorption of additives following the reverse current.

Fig.2: Partial fill as a function of feature size after 50nm of copper deposition in the field

Accelerator pretreatment:
In the typical electroplating sequence, accelerator species present in the plating bath begin adsorbing on the copper surface within features upon immersion of the wafer in the plating bath. As plating proceeds, the adsorbed accelerators are electrochemically reduced to more active species and concentrate within features as surface area decreases due to conformal growth. This leads to bottom-up fill. It is also possible to generate bottom-up fill by pre-treating the wafer surface with accelerating species and then plating in a highly levelling bath with little or no accelerator present. Using this approach, the accelerating activity yielding bottom-up fill is derived entirely from the surface coverage of accelerator achieved during pre-treatment, and is most effective during the early stages of plating when small and intermediate size features are filled. As plating proceeds, the levelling characteristics of the bath itself become dominant, thus resulting in elimination of overplating. Without pre-treatment, plating in the highly levelling baths yields conformal growth or slow bottom-up fill which results in centre voids in aggressive structures. Concerns with this approach, however, include attack or dissolution of marginal seed during accelerator pretreatment and introduction of defects associated with a new process step.

Sequential plating baths:
The initial bottom-up acceleration needed for filling and the subsequent levelling mechanisms required to yield a planar topography arise from fundamentally different properties of the electroplating bath. It is therefore possible to separate the plating process into sequential filling and levelling steps that are carried out in separate baths. Using this scenario, plating is initially performed in a bath with little or no leveller present which results in strong bottom-up fill acceleration. After small features are filled, the wafer is transferred to a bath with strongly levelling properties to stop the accelerated fill over dense trenches. If the wafer is transferred to the levelling bath before overplating becomes significant in the bottom-up acceleration bath, then improved deposit planarity can be obtained. Selecting an appropriate time for wafer transfer between plating baths can be difficult. If the transfer is carried out when only the smallest features have filled, then subsequent deposition in a levelling bath can result in centre voids in larger features not filled in the initial deposition step. If, however, the transfer is delayed until the intermediate size features are filled, then significant overplating will have already been generated over the smallest features in the highly accelerating bath. This trade-off leads to difficulty in achieving both good bottom-up fill in intermediate size features and reduced overplating on the smallest features.

Slowly accumulating levellers

Traditional levellers reach the copper surface at a rate determined by local solution mass transfer characteristics. These levellers rapidly adsorb and decrease the local deposition rate. Normally, the surface concentration of levellers quickly reaches a steady state as the adsorption rate of the levellers is offset by their electrolytic decomposition or incorporation in the plated film. If a leveller molecular structure is selected such that the leveller is neither rapidly incorporated in the film nor electrolytically decomposed, then levelling activity can gradually be increased during the period of filling. Using this approach, the filling of small and intermediate size features takes place over the same time period as the increase of levelling activity on the wafer surface. This approach combines the filling of small features under highly accelerating leveller-free conditions with subsequent plating under more strongly levelling conditions in a single bath.

The overplating and fill results obtained using this approach are compared in Figure 3 to fill and overplating results obtained using traditional levellers at low and high concentrations. At high concentration of traditional levellers, overplating of approximately 700Å is achieved, but a relatively low bottom-up fill rate is observed. This can lead to centre voids in 65nm generation features and limits the extendibility of such baths. The highly accelerating bath using low concentration of traditional levellers yields the very rapid bottom-up growth necessary for void-free filling of 65nm structures, but overplating is increased by about a factor of three creating CMP compatibility problems.

Fig.3: Rate of bottom-up filling and overplating height measured using plating baths containing traditional levellers with a low accelerator concentration (good levelling bath), traditional levellers with a high accelerator concentration (good bottom-up fill acceleration bath) and new levellers that gradually accumulate along with a high accelerator concentration (good fill and levelling bath)

Using a single bath consisting of non-traditional gradually accumulating levellers, and relatively high concentration of accelerator additives, both rapid fill acceleration and very low overplating of the order 600Å are obtained on typical structures. This approach meets the fill requirements for 65nm generation structures, is compatible with CMP, and provides a simple one bath, one step, electroplating process for high volume production.

This single step plating processes using a highly accelerating bath with levellers that become active only as filling is completed appears to provide the most simple and cost-effective means of 65nm generation fill with reduced overplating topography.

References:

1. R Rosenberg, D Edelstein, C Hu, K Rodbell, Annu. Rev. Mater. Sci., 30(229)2000.

2. J Reid, Jpn. J. Appl. Phys., 40(2650)2001.

3. R Binstead, J Calvert, R Mikkola, J Reid, J Sukamto, Seimiconductor Fabtech, p. 115, 20th edition, December, 2003.

4. C Hsieh, S Chou, S Shue, C Yu, M Laing, Proc. 2000 IITC Conf., p. 182.

5. T Moffat, D Wheeler, C Witt, D Jossel, Electrochem. And Solid - State Lett. , 5(110)2002.