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Making Sacrifices For Improved CMP

CMP is in widespread use in the semiconductor industry, but is also the source of many process integration concerns. Jeremy W McCutcheon of Brewer Science describes his company's Con-Tact planarisation technique to address many of these problems

CMP is in widespread use in the semiconductor industry, but is also the source of many process integration concerns. Jeremy W McCutcheon of Brewer Science describes his company's Con-Tact planarisation technique to address many of these problems


The development of chemical mechanical planarisation (CMP) in the late 1980s provided considerable improvements over previous techniques. It enabled global planarisation of the silicon wafer and is integral to the damascene metallisation processes used today.

While CMP has matured in the past decade and is now well-understood and established in IC production, it is not without its drawbacks. Poor local planarisation caused by pattern density variations, and difficulty planarising over different pattern densities, limits the technology. Of equal concern to many producers is the fact that CMP is a "dirty" process that involves abrasive materials, and which must be physically separated from other fabrication areas to avoid contamination. This creates difficulties in integrating CMP into the production process. It can also be highly wasteful, consuming expensive polishing materials and large amounts of water.

A new process from Brewer Science trademarked as CON-TACT seeks to address these issues and to provide an alternative technology that is clean, cost-effective and more easily integrated with automation.

Flatness transfer

The CON-TACT process is designed for use in planarising substrates, primarily in the integrated circuit industry and is based on the following steps:

* applying a sacrificial planarisation coating to a substrate

* pressing this coating layer against an optically flat surface

* using either an etch-back or CMP process to transfer the flatness of the planarisation material to the substrate layer(s)

In the past, etch-back processes have been used extensively for planarising dielectric materials. However, poor local planarisation caused by pattern density variations has imposed limitations on this technology. CMP also has difficulty planarising over different pattern densities. This manifests as dishing and erosion, both of which can be seen when using CMP over isolated and dense pattern areas in integrated circuit designs. When using the new press step, however, planarisation of the sacrificial material is unaffected by pattern density.

When etch-back and CMP are coupled with the press planarisation technology, improved results can be obtained while lowering the burden associated with both processes.

Evaluation

The sacrificial material used in the CON-TACT process is a low viscosity polymer. This is applied by spin coating followed by pressing using the CON-TACT tool (Figure 1) and process. To remove the underlying topography, the substrate undergoes anisotropic plasma etch, which provides both local and global planarisation.


















Fig.1: Automated Con-Tact tool




The performance of this technology can be illustrated in the following experimental set up which was used to planarise a dielectric topography substrate [1]. The wafers had varying line densities from 0% to 96% on a blanket PETEOS layer over a patterned nitride/aluminum/titanium-nitride stack. The topography measured approximately 1.0µm.

The sacrificial material was spin coated on to the dielectric wafer under process conditions that gave a 1.85µm film thickness on flat silicon wafers. Following the spin coating, the wafer was placed in the press chamber and the chamber evacuated to about 500mTorr. This step serves to remove residual solvents and volatiles, and to prevent bubble entrapment during the press step. When the chamber evacuation was complete, the substrate was pressed against the optically flat surface for 15-60secs.

Then, before separation, the material was cross-linked with heat or light. It is critical that the material be hardened prior to separation to prevent disrupting the surface. Figure 2 shows the general process flow for press planarisation.
















Fig.2: General process flow for press planarisation


To evaluate planarisation performance, topography measurements were taken with a Dektak8 surface profilometer. Measurements were made on:

* an uncoated control wafer

* a wafer coated with the sacrificial material and UV-cured without the press step

* a substrate coated and pressed

Data in Figure 3 show the densities from 20% to 76% for the coated but not pressed substrate and the press-planarised substrate. The control substrate shows the original topography with a step height of about 0.90µm.
















Fig.3: Dektak8 topography scans


The substrate with the coated, but not pressed, sacrificial material indicates good local planarisation within a particular density cell with a variation of less than 500Å. However, global planarisation between different densities is quite poor for the un-pressed substrate. The range between 20% and 76% density gives a variation in topography of about 4000Å.

In the case of the press-planarised sacrificial material coating, both local and global variations are held to about 400Å, which is 10 times better than for spin coating alone.

Work indicates that press planarisation has the capability to provide both local and global planarisation. In addition, on some of the most difficult structures that show large pattern density effects for CMP processing [2], the press planarisation process shows little pattern density effect. This method holds promise for a planarisation process that is truly independent of pattern density.

Further development

Work at Brewer Science continues with a focused effort on planarisation performance of the sacrificial materials through the process. The tooling automation has been completed, which allows for defect studies and long-term lifetime analysis of all components, materials, and processes. We are also scaling the process to 300mm substrates and reducing defect levels. In addition, this approach is being studied in conjunction with some CMP processes to remove undesirable effects. In the previously described process, CMP may be able to complement or replace the etch-back step.

Continuing developments will provide a range of materials and processes to cover the wide range of substrate layers that require planarisation. Materials include oxide dielectrics, low-k dielectrics, silicon, aluminum and tungsten. Work is also being conducted for the others uses of this concept. These include:

* direct planarisation of dielectric materials such as spin-on glasses for subtractive metal applications

* low-k dielectrics for eliminating dishing and erosion errors in Cu CMP resulting in impacts on subsequent layers

* BCB (Dow's CYCLOTENE product) planarisation for use in GaAs device dielectric and in wafer-level packaging applications



References:

1. SKW Associates, materials provided through their Web site, www.testwafer.com

2. Dale Hetherington, "CMP: Future Needs and New Applications", Planarization for ULSI Multilevel Interconnection - Short Course, March 2001, Santa Clara, CA



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