Info
Info
News Article

More Than Just A Package - Wafer-level Packaging Of MEMS

Packaging micro-electro-mechanical devices is less generic than IC assembly processes. IMEC scientists review trends in MEMS packaging

Packaging of micro-electro-mechanical devices differs from that of ICs because of the less generic nature of MEMS. Such packaging must address different and more diverse needs. Cost and miniaturisation drive the technology to more compact, wafer-level processed packaging schemes that can be applied to a wide range of devices. Subsystem integration makes increasing use of advanced, compact techniques such as chip stacking and multi-chip modules. IMEC scientists review some recent trends in MEMS packaging solutions, in particular, wafer-level packaging (WLP).


Micro-electro-mechanical systems (MEMS) are miniaturised systems with electrical as well as non-electrical (e.g. mechanical, optical and (bio)chemical) components. They will be indispensable parts of the intelligent devices of the future because they can add new functionalities or supply energy. But compared to IC development, interactions between technology, component and application are more complex in these systems. Concurrent engineering - addressing modelling, simulation, technology, packaging and reliability in parallel - is therefore essential.

The packaging of MEMS is a determining factor in their functional behaviour as well as in their production cost. A MEMS package typically has to fulfil the requirements of an IC package and must provide additional functionalities that are usually application specific (Figure 1). To provide cost-effective solutions, the MEMS community therefore is faced with the challenge to develop packaging schemes that can be applied to a wide range of MEMS devices.


















Fig.1: Functionalities of packaging ICs (top) vs. MEMS (bottom).






MEMS vs. IC packaging

The goal of IC packaging is in essence to provide physical support and an electrical interface to the chip and to isolate the chip physically from its environment. MEMS devices on the other hand are often interfaced intimately with their environment and are less generic in nature. Consequently, the packaging of MEMS has to address different and more diverse needs than IC packaging:

* MEMS do not obey scaling laws as ICs do: although some devices have been scaling down, MEMS are dealing with energy as input or output, and therefore scaling does not result in the same advantages as for ICs.

* There is a larger variety of basic building blocks in MEMS: sensors and actuators can be composed of pyroelectric, resistive, thermoelectric, magnetic, acoustic, chemical, optical . . . elements.

* There is often no dominant 'mainstream' process sequence for a particular building block.

* The packaging functionalities are inherently broader. IC packages have to accommodate ever-denser electrical I/Os and increasing levels of electrical power and thermal dissipation. Ambient parameters, such as moisture or pressure, are treated as non-desirable noise signals to be totally isolated from the IC by the package. In MEMS packaging, the electrical I/O is typically unidirectional and less dense. The electrical and thermal power handling is less demanding, but at least one of the non-electrical influences becomes a desired input.

Due to the additional packaging requirements, the classification of traditional IC packaging into at least four hierarchical levels of packaging is less applicable to MEMS. While 0-level packaging for ICs comprises the interconnection of numerous transistors, gates or cells within the chip itself (i.e. operations on the wafer level), 0-level or wafer-level packaging of MEMS encompasses all wafer-level operations (e.g. operations in which at least one full wafer is involved). 1-level packaging is performed after the individual MEMS devices and ICs have been extracted from the wafer.

Trends in MEMS packaging

Being less generic in nature, MEMS processes will presumably never reach the high degree of standardisation of CMOS ICs. Roadmaps for MEMS wafer processing and MEMS packaging are therefore less mature and less useful than their IC counterparts. Still, four major trends in MEMS packaging and subsystem integration can be derived, based on the two main drivers for current MEMS development, namely cost reduction and miniaturisation:

* more compact hybrid IC technology - MEMS integration and packaging concepts

* increased use of thin-film, wafer-level packaging and system integration concepts

* growing synergies between MEMS manufacturing equipment and IC/MEMS packaging equipment

* trend towards low-temperature technologies that can be applied on a variety of substrates including IC wafers, glass and laminate

Zero-level packaging concepts

MEMS in wafer form are typically extremely sensitive to their environment until they are packaged. They often contain fragile parts that can be damaged during back-end operations such as dicing, pick-and-place, wire-bonding and soldering or during exposure to particles. As such, a protection in an early stage of the package process is required. Therefore, the 0-level (and/or 1-level) package often contains a 'capping' function of the MEMS (Figure 2). This cap can additionally act as a structural part for those MEMS devices that require operation in a vacuum, at reduced pressure or in an inert ambient. For certain devices - such as microrelays or micro-accelerometers - the ambient of the cavity housing the MEMS device can play a very important role in tuning the operating characteristics. Further, it is evident that the impact of the cavity realisation process on the device performance must be reduced to a minimum. This often necessitates low-temperature processing and the absence of any aggressive or corrosive agents during sealing. Of course, the cost of manufacturing must be reduced as much as possible, since packaging is a determining factor for the production cost of MEMS.




















Fig.2: Capping of the MEMS device as part of the packaging sequence.







Three approaches for realising the encapsulation are currently in use: wafer-to-wafer bonding, die-to-wafer bonding and surface micromachining.

The general idea of wafer-to-wafer bonding is to cap the wafer containing the MEMS structures with a separate, micromachined wafer in which a (small) cavity is made or a stand-off ring is implemented (Figure 3). As such, a stack of wafers can be built. For the bonding of the wafer, several methods exist, the most prevailing techniques being anodic, fusion or glass frit sealing. The process and materials employed determine the hermeticity and controllability of the cavity ambient. The approach is well established and dedicated equipment with high throughput and yield is commercially available. The main disadvantages of the method are the additional processing required for bond pad access, the limited topography that can be allowed for feed-through signal lines, and (especially in the case of fusion bonding) the high process temperatures. However, recent developments using polymeric sealing materials and wafer-thinning techniques are very promising for overcoming these barriers.


















Fig.3: MEMS wafer with wafer-to-wafer caps. After bonding, the cap wafer with preprocessed cavities is separated by wafer thinning.





Die-to-wafer bonding offers a competitive alternative. Preprocessed and diced caps are placed one by one on each MEMS device on the wafer by means of a flip-chip bonder. Especially in case of larger dies, the approach offers economical advantages over wafer-to-wafer bonding. For larger dies, the longer bonding process time due to the mounting of individual caps is balanced by the fact that bond pads are readily accessible. The technique can be used for low-temperature sealing materials, including solder seals, with hermeticity below 10-11mbar.l/s. It can be used for thin caps as well. A cost-effective way of controlling the inner ambient is IMEC's Indent Reflow Sealing (IRS) technique [1]. The method is based on wafer bonding whereby the chips are flip-chip assembled using a solder bond. An optional spacer layer is implemented underneath the solder layer to allow better control of the cavity height. Key steps in the IRS technique are the creation of an indent, plasma pre-treatment (to ensure a clean cavity), pre-bonding without closing the indent, and closing of the indent during the solder reflow step in a designated oven. The method provides both hermeticity of the cavity seal and controllability of the cavity ambient, two features essential for packaging MEMS. In addition, the technique has potential application for MEMS device packaging in which a great flexibility with respect to the cavity pressure and ambient is required. Other advantages of IRS are the use of low bonding temperatures (220-350°C) and the ability to seal large batches of chip-on-wafer (or chip-on-chip) simultaneously, rendering the method cost-effective with a high throughput.

The most compact way of hermetic sealing is to make use of thin-film caps realised by surface micromachining (Figure 4). In this approach, the cavity contains an access channel for the sacrificial layer etchant. After completing the sacrificial layer etch, the channel is closed, thereby sealing the cavity. Closing the channel is conveniently done using reactive sealing techniques, for instance, by growing a conformal LPCVD layer or simply by covering up the hole. As compared to the other approaches, the horizontal dimensions of the cap can be shrunk to essentially the area of the MEMS device underneath, and the cap thickness can be reduced to less than 50µm.




















Fig.4: Encapsulation by thin film. A membrane of poly-Si(Ge) is surface-micromachined over the MEMS device and subsequently hermetically sealed.







This technique is the most complex one, but a noticeable advantage relates to the fact that a number of wafers can be sealed simultaneously. The choice of the cap material and sacrificial layer is to some extent specific to the MEMS device underneath, implying relatively high non-recurring development costs. In mass production of MEMS devices, the increased development effort can be offset by lowered production costs due to extended use of wafer-scale processing and savings in MEMS real estate.

Subsystem integration

MEMS packaging is not limited to the packaging of individual MEMS devices. It also encompasses the integration of MEMS into systems. This subsystem integration can in several cases be realised by conventional wire-bonding and mounting into standard packages, but more and more compact packaging schemes such as chip stacking and integration in multi-chip modules are being developed for complex MEMS demands.

Chip stacking is applied for interconnecting high-density imagers, displays, or inkjets with hundreds of thousands of pixels to their addressing and read-out ASICs.

RF-MEMS devices such as switches and resonators are being integrated with passive RF components in a multi-layer thin-film module technology (MCM-D), resulting in true RF systems-in-a-package. These MCM-Ds are formed by the deposition of thin-film metals and dielectrics, either polymers or inorganic dielectrics, on dimensionally stable bases such as silicon, glass or ceramic. The MCM-D technology enables the integration of passive components into the substrate or assembled in discrete form on the substrate. The adaptation of the RF-MEMS technology towards an MCM-D platform allows an optimisation of the performance of RF switches and variable capacitors. Also other components can be integrated in such a platform.



References:

1. E Parton, and H Tilmans, Wafer-level MEMS packaging, Advanced Packaging, Vol.11, No.4, pp.21-23, 2002.

Authors:

K Baert, P De Moor, H Tilmans, J John, A Witvrouw, C Van Hoof, E Beyne, IMEC, Leuven.



AngelTech Live III: Join us on 12 April 2021!

AngelTech Live III will be broadcast on 12 April 2021, 10am BST, rebroadcast on 14 April (10am CTT) and 16 April (10am PST) and will feature online versions of the market-leading physical events: CS International and PIC International PLUS a brand new Silicon Semiconductor International Track!

Thanks to the great diversity of the semiconductor industry, we are always chasing new markets and developing a range of exciting technologies.

2021 is no different. Over the last few months interest in deep-UV LEDs has rocketed, due to its capability to disinfect and sanitise areas and combat Covid-19. We shall consider a roadmap for this device, along with technologies for boosting its output.

We shall also look at microLEDs, a display with many wonderful attributes, identifying processes for handling the mass transfer of tiny emitters that hold the key to commercialisation of this technology.

We shall also discuss electrification of transportation, underpinned by wide bandgap power electronics and supported by blue lasers that are ideal for processing copper.

Additional areas we will cover include the development of GaN ICs, to improve the reach of power electronics; the great strides that have been made with gallium oxide; and a look at new materials, such as cubic GaN and AlScN.

Having attracted 1500 delegates over the last 2 online summits, the 3rd event promises to be even bigger and better – with 3 interactive sessions over 1 day and will once again prove to be a key event across the semiconductor and photonic integrated circuits calendar.

So make sure you sign up today and discover the latest cutting edge developments across the compound semiconductor and integrated photonics value chain.

REGISTER FOR FREE

VIEW SESSIONS
SUSS MicroTec Opens New Production Facility In Taiwan
New Plant To Manufacture Graphene Electronics
South Korean Point Engineering Chooses ClassOne’s Solstice S8 For Advanced Semiconductor Plating
Panasonic Microelectronics Web Seminar
GOODFELLOW Confirms Membership In The BSI UK Graphene Group
Tower Semiconductor Announced Program Creating An Integrated-Laser-on-Silicon Photonics Foundry Process
Siemens And ASE Enable Next-generation High Density Advanced Package Designs
EV Group Establishes State-of-the-art Customer Training Facility
Onto Innovation Announces New Inspection Platform
Cadence Announces $5M Endowment To Advance Research
Can New Advances In CMOS Replace SCMOS Sensors In Biomedical Applications?
Belgian Initiative For AI Lung Scan Analysis In Fight Against COVID-19 Goes European
Tescan And 3D-Micromac Collaborate To Increase The Efficiency Of Failure Analysis Workflows
Changes In The Management Board Of 3D-Micromac AG
ASML Reports €14.0 Billion Net Sales
Imec Demonstrates 20nm Pitch Line/Space Resist Imaging With High-NA EUV Interference Lithography
U.S. Department Of Defense Partners With GLOBALFOUNDRIES To Manufacture Secure Chips At Fab 8
K-Space Offers A New Accessory For Their In Situ Metrology Tools
ITRI And DuPont Inaugurate Semiconductor Materials Lab
Will Future Soldiers Be Made Of Semiconductor?
DISCO's Completion Of New Building At Nagano Works Chino Plant
TEL Introduces Episode UL As The Next Generation Etch Platform
AP&S Expands Management At Beginning Of 2021
Obducat Receives Order For Fully Automated Resist Processing Tool From A Customer In Asia

Info
×
Search the news archive

To close this popup you can press escape or click the close icon.
Logo
×
Logo
×
Register - Step 1

You may choose to subscribe to the Silicon Semiconductor Magazine, the Silicon Semiconductor Newsletter, or both. You may also request additional information if required, before submitting your application.


Please subscribe me to:

 

You chose the industry type of "Other"

Please enter the industry that you work in:
Please enter the industry that you work in:
 
X
Info
X
Info
{taasPodcastNotification} Array
Live Event