Removing Metal Gate Process Residues
Cleaning residues from processing is a key step in semiconductor production. New transistor gate materials are due in the near future with the use of High-K Gate insulationand metal rather than polysilicon gate electrodes. Researchers from IMEC and Spin Processor tool producer SEZ consider the implications of such new materials for cleaning.
The 2003 update to the International Technology Roadmap for Semiconductors (ITRS) identifies replacement of the gate oxide (GOX), SiO2, as one of the grand challenges in the next several years . Due to the resulting reliability issues from tunnelling and gate leakage currents through the use of thin (<2nm) GOX, high-k materials will be required. This will enable the use of a layer with a much larger physical thickness for an identical equivalent oxide thickness (EOT).
However, the use of high-k has the knockon that the polysilicon gate electrodes on top of the GOX replacement in complementary metal oxide semiconductor (CMOS) transistor structures exhibit undesirable qualities such as carrier depletion and boron out-diffusion. Poly depletion contributes to increased EOT values. In consequence, it is believed that dual-metal gate electrodes will be needed to replace polysilicon by 2007. Some of the more favoured candidate materials are metallic compounds such as TaN and TiN [2, 3].
The implementation of such new materials into the process flow - especially at the front end of line (FEOL) - presents many challenges related to cleaning. In order to prevent cross-contamination between wafers in shared tools (metrology, lithography, etc.), it is necessary to remove high-k and metal residues from the backside and bevel of the wafer.
Wafer spin-processor cleaning systems, such as those produced by SEZ, can be used to clean TiN, TaN and residues from mixed gate stacks on the backside, bevel and a defined region on the front side of the wafer.
Spin cleaning experiments have been performed on various stacks of blanket films that were deposited on Czochralski-grown (CZ) p-type <100> 200mm silicon wafers.
Three stack structures were processed:
● physical vapour deposited (PVD) TiN or TaN on a Si3N4/SiO2 stack (50nm LPCVD Si3N4/250nm DXZ CVD SiO2/100nm PVD TiN or TaN)
● PVD TiN or TaN on nitrided SiO2 (3.5nm nitrided SiO2/10nm PVD TiN or TaN/100nm poly-Si)
● poly-Si on PVD TiN or TaN on HfO2 (4nm CVD HfO2/10nm PVD TiN or
The wafers were processed using the backside & bevel clean technique , on a SEZ SP203 wafer spin-processor system to remove TiN, TaN and other residues from mixed gate stacks. In the last two stacks, the wafer backside was also protected with layers consisting of 15nm SiO2/20nm Si3N4.
Etch rates of 100nm metal gate blanket wafers were preliminarily determined by beaker tests with wafer pieces using a threefactor mixture design (Design Expert v.6.0.3) with varying percentages of aqueous hydrofluoric acid (HF), nitric acid (HNO3) and ultrapure water.
The optimal etch mixture, as well as additional chemistries, were then evaluated on a single-wafer spin processor of SEZ. In this tool, the wafers are placed such that the process side is face up on a Bernoulli chuck. During the entire etch process the wafer floats on a nitrogen cushion without touching the rotating chuck - this allows wafers to be processed on one side without damaging the other. The chuck design permits a small amount of chemistry to wrap around the wafer to additionally clean the bevel and a defined area on the wafer front side. The depth of the removed zone on the wafer front side can be adjusted individually. For the results presented, 1.5mm, 3mm and 3.5mm edge clearances were chosen. The chemistry can be run in re-circulation or single-pass mode. For the purposes of the work described here, the chemistry was recirculated. In the tests to verify complete removal of the metal gate, the front sides of the wafers were etched so that a total reflection x-ray fluorescence (TXRF) spectrometer could be used for contamination measurements. For these tests, wafers with TiN/TaN on nitrided SiO2 were etched down to the SiON. By using a thin SiON as gate dielectric, the wafers could be measured with a standard Si-calibration on the TXRF equipment. Moreover, a better detection limit for Ti and Ta was achieved compared to wafers having high-k instead of SiON, because interference - for example, between Hf and Ta - was avoided.
The undercut profiles of the step height edge removal on the wafer front side were measured with a Tencor P-2 long scan profiler. The sheet resistances of the TiN and TaN layers were measured using a Tencor OmniMap RS75/tc. A Leitz Ergolux microscope equipped with CCD was usedfor optical measurements. A Philips XL810 was used for SEM measurements. A TXRF 8300W from Atomika-FEI with MoKα excitation was used to measure the trace concentration of Ti and Ta on the wafers. A light scattering measurement system - a KLA-Tencor SP1DLS - was used for particle measurements on the wafers.
The initial etch rate evaluations were conducted on wafers with a thicker (100nm) layer of the various metal gate materials without an additional layer of polysilicon. Recognising that metal gate wafers could additionally include a polysilicon layer, the preliminary screening designs were conducted to determine if a polysilicon etchtype solution (HNO3/HF/H2O mixture) could be used as a single-pass chemistry to provide the desired backside removal, as well as bevel and defined edge clean of the mixed metal residues. It was found that the etch rate of TiN was much lower than TaN and both were less than polysilicon.
Due to the considerable etch rate difference between TiN and poly-Si, a long over etch of the poly-Si would be required to remove all TiN residue from wafers with a TiN/poly-Si gate. To avoid the risk of damaging the backside, a two-chemistry solution was investigated. The target was to remove the poly-Si in a first step and then selectively remove the TiN. The APM-based chemistry of NH4OH/H2O2/H2O at elevated temperature provided good etch selectivity between TiN and poly-Si.
Moving on to the wafers with pure metal gates on silicon nitride/CVD oxide, first the backside and bevel were cleaned. A HNO3/HF-based solution was formulated to provide complete removal of the TiN or TaN residues from the wafer bevel and the 3mm defined region on the wafer front side (Figure 1).
The next set of wafers included a thin layer of as-deposited (unannealed) HfO2 as the gate dielectric with a TiN/poly-Si gate on top. With a second material present at the bevel, the clean of the front side edge has to be carefully controlled to avoid an under etching of the top layer. If the wraparound etch of the TiN or TaN is deeper than the etch of the poly-Si, the risk of fracturing some of the poly-Si and subsequently creating particles could be very high.
A similar HNO3/HF-based chemistry as previously used was able to remove the poly-Si and TaN residue from the backside, bevel and 3.5mm defined edge of these wafers. The edge profile was again well defined without any undercutting of the upper poly-Si layer (Figure 2). The complete removal of the Ta residue from the wafer was demonstrated by TXRF measurements.
Due to the etch rate differences between TiN and polysilicon, a two-chemistry recipe was used to etch the HfO2/TiN/poly-Si wafers.
The polysilicon residue was removed in a first step using a HNO3/HF-based chemistry and the underlying TiN residue was subsequently removed selectively without additional attack on the polysilicon using the APM-based chemistry (Figure 3). The effectiveness of this chemistry to remove Ti residues was demonstrated using wafers with a nitrided SiO2 gate material and subsequent TXRF measurements.
A comparison of SP1 measurements (Figure 4) pre- and post-processing demonstrated that the active area was well protected with only about 20 particle adders greater than 0.1µm LSE.
As previously noted, it was hoped to use one chemistry to remove the polysilicon, as well as the metal gate material, from wafers containing both materials.
The HNO3/HF chemistry mixture was similarly applied to wafer stacks with a thinner layer of the metal gate (to be used as the work function material) capped with 100nm of polysilicon. This chemistry was able to remove both the polysilicon and TiN gate materials from the wafer bevel and a 1.5mm defined region on the wafer front side.
The edge profile (Figure 5) revealed that both materials were removed with the formation of a single step without undercutting the polysilicon layer.
The effective removal of the Ti and Ta residues from the wafer surfaces was demonstrated by removing first the poly-Si and then the TiN (or TaN) layer from the front side of the Si/SiON/TiN(TaN)/poly-Si wafer stack and measuring the contamination levels with straight TXRF. The metal gate residues could be reduced to below the detection limits of the TXRF measurements. (Table 1)
Jim Snow, Wim Fyen, Paul W Mertens, IMEC. Harald Kraus, Frederic Kovacs, SEZ. Kenneth Vermeyen, Katholieke Hogeschool Limburg.
1. International Technology Roadmap for Semiconductors 2003 Update, Table 71a, p.59.
2. CH Lee, YH Kim, HF Luan, SJ Lee, TS Jeon, WP Bai, and DL Kwong, 2001 Symp. VLSI Tech. Digest of Technical Papers, p.137, (2001).
3. D Lammers, Silicon Strategies, 11/26/2002.
4. PS Lysaght and M West, Solid State Technology, November 1999.