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News Article

Strain across wafer to deliver new possibilities

European companies Soitec and ASM International claim a major breakthrough in their joint development effort to combine the speed/performance benefits of strained silicon with the power/performance benefits of silicon-on-insulator (SOI) technology with “wafer-level” strain.
European companies Soitec and ASM International claim a major breakthrough in their joint development effort to combine the speed/performance benefits of strained silicon with the power/performance benefits of silicon-on-insulator (SOI) technology with “wafer-level” strain.

Soitec has been sampling 200mm sSOI wafers since Q2 2003, and is currently upgrading its 300mm sSOI production line - the first of its kind - for sampling and pilot manufacturing. Early sSOI sampling will enable the IC industry to explore this path to improved performance and to meet the emerging needs for the 65nm node and beyond.

Soitec and ASM believe that this capability will extend the technology advantages well beyond the highly publicised “local strain” in use today.

A yearlong collaborative effort has resulted in an unprecedented quality of the strained layer with reduced the defectivity levels to between 100 and 1000 times lower than the industry standard, bringing sSOI quality close to that of standard SOI and bulk silicon. As wafer-level strain is not dependent on IC design, sSOI substrates will enable a wider range of high-speed, low-power IC applications, including those with high-performance logic cores, the partners believe.

The work has combined Soitec's patented Smart Cut technology with ASMs low-temperature-enhanced 300mm Epsilon 3200 reactor and A412 vertical furnace. Smart Cut ensures that the target high-quality epitaxial strained layer is split from the underlying high-defectivity epitaxial template and transferred to a host silicon wafer to form sSOI.

Dr Carlos Mazure, Soitec's chief technology officer, reports: “Our customer and internal evaluations show that the strain of sSOI is very robust, surviving the typical thermal budgets of 65nm CMOS processes.”

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