Leti gate stack research looks to Tokyo Electron
The research will seek the new materials necessary to overcome CMOS gate stack challenges in terms of high-k dielectric and metal electrodes for 45nm and below nodes of the International Technology Roadmap for Semiconductors (ITRS). The work will be based at CEA Leti's new 300mm facility, Nanotec300, in Grenoble, France.
TEL will provide its TELFORMULA flexible batch thermal processing system and single-wafer Trias system for processing the gate stacks. The batch system will be used to deposit high-k dielectrics. The single-wafer tool will integrate a proprietary metal deposition chamber. Another chamber will be devoted to the surface treatment of these materials. In addition to the basic development of these materials, the JDP will address pre- and post-processes for the whole CMOS gate stack module.
The Nanotec300 facility is also under a four-year contract with the three semiconductor manufacturing partners of the Crolles Alliance – Freescale Semiconductor (ex Motorola), Philips and STMicroelectronics.
