SUSS to develop tool for IBM package process
As part of the technology and licensing pact, SUSS MicroTec will develop a complete line of 300mm and 200mm tools to enable commercialisation of C4NP. For its part, IBM will continue advanced research and process optimisation of C4NP and offer on-site process training to customers who purchase commercial systems from SUSS MicroTec.
C4NP uses wafer solder bump technology, a semiconductor packaging technique which places pre-patterned solder balls onto the surface of a chip. These bumps ultimately carry data from individual chips to the rest of a computing system via a complex arrangement of intricate wiring and materials. C4NP allows the creation of pre-patterned solder balls to be completed while a wafer is still in the front-end of a manufacturing facility, potentially reducing cycle time.
The solder bumps can be inspected in advance and deposited onto the wafer in one simple step using technology similar to wafer-level bonding. The technology employs the simplicity of solder paste processing (stencil/screen), but instead uses pure molten alloy to produce the fine pitch capability of electroplating. Parallel processing allows increased efficiency and advanced quality control for wafer bumping.
C4NP also easily accommodates binary, ternary and quaternary alloys and minimises the recurring and additive costs of consumables since only the solder balls are created and transferred to the wafer without waste. C4NP is not dependent on wafer size, allowing 200mm and 300mm wafers to be processed with similar efficiency. Additionally, C4NP has achieved technical capability well beyond the International Technology Roadmap for Semiconductors (ITRS) specification for packaging technology, the companies report.
