Stained SOI for partially-depleted architectures
The company reports that customer and internal evaluations show that the PD-sSOI is a robust solution that meets the processing requirements of the 65nm and smaller technology nodes. Samples have been offered to development partners. Production samples will be available throughout 2005 with full-volume production due in H2.
Soitec believes that its new product will allow global chipmakers to achieve up to an 80% improvement in the electron mobility on future chips without significant process changes or any of the yield concerns associated with germanium-based strained SOI technologies.
Soitec's president and CEO Andre Auberton-Herve comments: "This is an ideal solution for both partially- and fully-depleted architectures, since it overcomes front-end-of-line integration and yield concerns associated with germanium, and thanks to wafer-level strain is no longer dependent on IC design."
Soitec plans to offer a complete portfolio of strained SOI engineered substrates to meet a broad range of requirements for both partially-depleted (more than 35nm thick) and fully-depleted (less than 25nm thick) architectures. The company has worked with semiconductor equipment supplier ASM International to develop this capability.
